MPC8313ZQADDC Freescale Semiconductor, MPC8313ZQADDC Datasheet - Page 662

• Manufacturer Part Number: MPC8313ZQADDC
• Description: Microprocessors - MPU 8313 REV2.2 PB NO ENC
• Manufacturer: Freescale Semiconductor

Specifications of MPC8313ZQADDC

• Processor Series: MPC8313
• Core: e300
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 133 MHz
• Program Memory Size: 16 KB
• Data Ram Size: 16 KB
• Interface Type: I2C
• Mounting Style: SMD/SMT
• Package / Case: PBGA
• Number Of Programmable I/os: 32
• Number Of Timers: 4

Security Engine (SEC) 2.2
The DEUMR is cleared when the DEU is reset or re-initialized. Setting a reserved mode bit will generate
a data error. If the mode register is modified during processing, a context error will be generated.
Table 14-11
14.4.1.2
The value of the DEU key size register (DEUKSR), shown in
of key memory that should be used in encrypting or decrypting. If the DEUMR is set for single DES, any
value other than 8 bytes will automatically generate a key size error in the DEU interrupt status register
(DEUISR). If the mode bit is set for triple DES, any value other than 16 bytes (112 bits for 2-key triple
DES (K1 = K3) or 24 bytes (168 bits for 3-key triple DES) will generate an error. Triple DES always uses
K1 to encrypt, K2 to decrypt, K3 to encrypt (any write to K1 duplicates that value into K3 in case 2-key
3DES is desired).
14-20
The following bits are described for information only. They are not under direct user control.
The following bits are controlled through the MODE0 field of the descriptor header.
56–60
0–54
Bits
55
61
62
63
Reset
Field
Addr
R/W
Name
CE
ED
TS
—
—
—
describes DEUMR fields.
0
DEU Key Size Register (DEUKSR)
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
Reserved
Reserved
Reserved
CBC/ECB. If set, the DEU operates in cipher-block-chaining mode. If not set, DEU operates in electronic
codebook mode.
0 ECB mode
1 CBC mode
Triple/Single DES. If set, the DEU operates the Triple DES algorithm; if not set, DEU operates the single DES
algorithm.
0 Single DES
1 Triple DES
Encrypt/decrypt. If set, the DEU operates the encryption algorithm; if not set, DEU operates the decryption
algorithm.
0 Perform decryption
1 Perform encryption
Figure 14-7. DEU Mode Register (DEUMR)
Table 14-11. DEUMR Field Descriptions
—
DEU 0x3_2000
R/W
Description
0
54
Figure
—
55
56
14-8, indicates the number of bytes
—
60
Freescale Semiconductor
CE
61
TS
62
ED
63