MPC8313ZQADDC Freescale Semiconductor, MPC8313ZQADDC Datasheet - Page 16

• Manufacturer Part Number: MPC8313ZQADDC
• Description: Microprocessors - MPU 8313 REV2.2 PB NO ENC
• Manufacturer: Freescale Semiconductor

Specifications of MPC8313ZQADDC

• Processor Series: MPC8313
• Core: e300
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 133 MHz
• Program Memory Size: 16 KB
• Data Ram Size: 16 KB
• Interface Type: I2C
• Mounting Style: SMD/SMT
• Package / Case: PBGA
• Number Of Programmable I/os: 32
• Number Of Timers: 4

Paragraph
Number
10.4.4
10.4.4.1
10.4.4.1.1
10.4.4.1.2
10.4.4.1.3
10.4.4.1.4
10.4.4.2
10.4.4.2.1
10.4.4.2.2
10.4.4.3
10.4.4.4
10.4.4.4.1
10.4.4.4.2
10.4.4.4.3
10.4.4.4.4
10.4.4.4.5
10.4.4.4.6
10.4.4.4.7
10.4.4.4.8
10.4.4.4.9
10.4.4.4.10
10.4.4.5
10.4.4.6
10.5
10.5.1
10.5.1.1
10.5.1.2
10.5.1.3
10.5.1.4
10.5.1.5
10.5.2
10.5.2.1
10.5.2.2
10.5.2.3
10.5.2.4
10.5.3
10.5.4
10.5.4.1
10.5.4.2
10.5.4.3
xvi
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
Initialization/Application Information ......................................................................... 10-88
User-Programmable Machines (UPMs)................................................................... 10-72
Interfacing to Peripherals in Different Address Modes ........................................... 10-88
Bus Turnaround ....................................................................................................... 10-91
Interface to Different Port-Size Devices.................................................................. 10-92
Command Sequence Examples for NAND Flash EEPROM................................... 10-93
UPM Requests ..................................................................................................... 10-73
Programming the UPMs ...................................................................................... 10-75
UPM Signal Timing............................................................................................. 10-77
RAM Array .......................................................................................................... 10-78
Synchronous Sampling of LUPWAIT for Early Transfer Acknowledge ............ 10-87
Extended Hold Time on Read Accesses .............................................................. 10-87
Multiplexed Address/Data Bus for 26-Bit Addressing........................................ 10-88
Non-Multiplexed Address and Data Buses.......................................................... 10-88
Multiplexed Address and Data to Save Maximum Pins in 8- to 16-Bit
Peripheral Hierarchy on the Local Bus for High Bus Speeds ............................. 10-89
GPCM Timings.................................................................................................... 10-90
Address Phase after Previous Read ..................................................................... 10-91
Read Data Phase after Address Phase ................................................................. 10-91
Read-Modify-Write Cycle for Parity Protected Memory Banks ......................... 10-92
UPM Cycles with Additional Address Phases..................................................... 10-92
NAND Flash Soft Reset Command Sequence Example ..................................... 10-94
NAND Flash Read Status Command Sequence Example ................................... 10-94
NAND Flash Read Identification Command Sequence Example ....................... 10-94
Memory Access Requests................................................................................ 10-74
UPM Refresh Timer Requests ......................................................................... 10-74
Software Requests—RUN Command ............................................................. 10-75
Exception Requests.......................................................................................... 10-75
UPM Programming Example (Two Sequential Writes to the RAM Array).... 10-76
UPM Programming Example (Two Sequential Reads from the RAM Array) 10-77
RAM Words..................................................................................................... 10-79
Chip-Select Signal Timing (CSTn) ................................................................. 10-82
Byte Select Signal Timing (BSTn) .................................................................. 10-83
General-Purpose Signals (GnTn, GOn)........................................................... 10-83
Loop Control (LOOP) ..................................................................................... 10-83
Repeat Execution of Current RAM Word (REDO) ......................................... 10-84
Address Multiplexing (AMX) ......................................................................... 10-84
Data Valid and Data Sample Control (UTA) ................................................... 10-85
LGPL[0:5] Signal Negation (LAST) ............................................................... 10-86
Wait Mechanism (WAEN) ............................................................................... 10-86
Addressing ....................................................................................................... 10-89
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