MPC8313ZQADDC Freescale Semiconductor, MPC8313ZQADDC Datasheet - Page 912

• Manufacturer Part Number: MPC8313ZQADDC
• Description: Microprocessors - MPU 8313 REV2.2 PB NO ENC
• Manufacturer: Freescale Semiconductor

Specifications of MPC8313ZQADDC

• Processor Series: MPC8313
• Core: e300
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 133 MHz
• Program Memory Size: 16 KB
• Data Ram Size: 16 KB
• Interface Type: I2C
• Mounting Style: SMD/SMT
• Package / Case: PBGA
• Number Of Programmable I/os: 32
• Number Of Timers: 4

Enhanced Three-Speed Ethernet Controllers
Table 15-166
Table 15-167
15-194
Set up the MII Mgmt for a write cycle to the external PHY Auxiliary Control and Status Register to configure the PHY through
ECGTX_CLK125
eTSEC Signals
MDIO
set source clock divide by 14 for example to insure that MDC clock speed is not greater than 2.5 MHz
MDC
describes the shared signals of the MII interface.
describes the register initializations required to configure the eTSEC in MII mode.
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
Sum
Writing to MII Mgmt Control with 16-bit data intended for the external PHY register,
(This example has Full Duplex = 0, Preamble count = 7, PAD/CRC append = 1)
the Management interface (overrides configuration signals of the PHY).
I/O
I/O
O
MACSTNADDR2[0110_0000_0000_0010_0000_0000_0000_0000]
MACSTNADDR1[0100_0011_0110_0101_1000_0111_1000_1100]
I
MIIMIND ---> [0000_0000_0000_0000_0000_0000_0000_0000]
MACCFG1[1000_0000_0000_0000_0000_0000_0000_0000]
MACCFG1[0000_0000_0000_0000_0000_0000_0000_0000]
MACCFG2[0000_0000_0000_0000_0111_0001_0000_0100]
Table 15-167. MII Mode Register Initialization Steps
MIIMCON[0000_0000_0000_0000_0000_0000_0000_0100]
MIIMCFG[1000_0000_0000_0000_0000_0000_0000_0111]
MIIMCFG[0000_0000_0000_0000_0000_0000_0000_0101]
MIIMADD[0000_0000_0000_0000_0000_0000_0001_1100]
ECNTRL[0000_0000_0000_0000_0001_0000_0000_0000]
Set station address to 02_60_8C_87_65_43, for example.
Set station address to 02_60_8C_87_65_43, for example.
Read MII Mgmt Indicator register and check for Busy = 0,
Signals
No. of
Perform an MII Mgmt write cycle to the external PHY
This indicates that the eTSEC MII Mgmt bus is idle.
Initialize MACCFG2, for MII, half duplex operation.
1
1
1
(This example has Statistics Enable = 1)
Table 15-166. Shared MII Signals
Reset the management interface.
Setup the MII Mgmt clock speed,
Initialize MAC Station Address,
Initialize MAC Station Address,
MII Signals
not used
MDIO
MDC
Initialize ECNTRL,
Clear Soft_Reset,
Set I/F Mode bit,
Set Soft_Reset,
Sum
I/O
I/O
O
I
Signals
No. of
1
1
0
Management interface clock
Management interface I/O
Reference clock
Function
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