MPC8313ZQADDC Freescale Semiconductor, MPC8313ZQADDC Datasheet - Page 512

• Manufacturer Part Number: MPC8313ZQADDC
• Description: Microprocessors - MPU 8313 REV2.2 PB NO ENC
• Manufacturer: Freescale Semiconductor

Specifications of MPC8313ZQADDC

• Processor Series: MPC8313
• Core: e300
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 133 MHz
• Program Memory Size: 16 KB
• Data Ram Size: 16 KB
• Interface Type: I2C
• Mounting Style: SMD/SMT
• Package / Case: PBGA
• Number Of Programmable I/os: 32
• Number Of Timers: 4

Enhanced Local Bus Controller
10.4.3.2.2
A NOP instruction that appears in FIR ahead of the last instruction is executed with the timing of a regular
command instruction, but neither LFCLE nor LFWE are asserted. Thus a NOP instruction may be used to
insert a pause matching the time taken for a regular command write.
10.4.3.2.3
Address instructions are used to issue addresses to the NAND Flash EEPROM. A complete device address
is formed from a sequence of one or more bytes, each written onto LAD[0:7] with LFALE and LFWE
asserted together. There are three kinds of address generation provided:
10.4.3.2.4
Data read instructions assert LFRE repeatedly to transfer one or more bytes of read data from the NAND
Flash EEPROM. Data read instructions are distinguished by their data destination:
10-64
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Column address—CA. A column address comprises one byte (ORn[PGS] = 0) or two bytes
(ORn[PGS] = 1) locating the starting byte or word to be transferred in the next page read or write
sequence. FPAR[CI] sets the value of the column index provided that FBCR[BC] is non-zero. In
the case that FBCR[BC] = 0, a column index of zero is issued to the device, regardless of the value
in FPAR[CI].
Page address—PA. A page address comprises 2, 3, or 4 bytes, depending on the setting of
FMR[AL], and locates the data page in the NAND Flash address space. The complete page address
is the concatenation of the block index, read from FBAR[BLK], with the page-in-block index, read
from FPAR[PI]. The page address length set in FMR[AL] should correspond with the size of
EEPROM being accessed. Similarly, the block index in FBAR[BLK] must not exceed the
maximum block index for the device, as most devices require reserved address bits to be written
as zero.
User-defined address—UA. This instruction allows the FCM to write a user-defined address byte,
which is read from the next AS field in MDR, starting at MDR[AS0]. Each subsequent UA
instruction reads an adjacent AS field in MDR, until all four AS bytes (MDR[AS0], MDR[AS1],
MDR[AS2], MDR[AS3]) have been sent; a fifth and any following UA instructions send zero as
the address byte. Note that each UA instruction advances the MDR pointer for writes by one byte,
and therefore a mix of UA and WS instructions can consume adjacent bytes from MDR.
Read data to buffer RAM immediately—RB. This instruction reads FBCR[BC] bytes of data into
the current FCM RAM buffer addressed by FPAR. If FBCR[BC] = 0, an entire page (including
spare region) is transferred in a burst, starting at the page boundary, and the ECC calculation is
checked against the ECC stored in the spare region. Correctable ECC errors are corrected and
reported in LTECCR[SBCE]; other errors may cause an interrupt if enabled. If the value of
FBCR[BC] takes the read pointer beyond the end of the spare region in the buffer, FCM discards
any excess bytes read.
Read data/status to MDR immediately—RS. This instruction asserts LFRE exactly once to read
one byte (8-bit port size) of data into the next AS field of MDR. Reads beyond the fourth byte of
MDR are discarded. The MDR read pointer is independent of the MDR write pointer used by UA
and WS instructions.
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
FCM No-Operation Instruction
FCM Address Instructions
FCM Data Read Instructions
Freescale Semiconductor