MPC8313ZQADDC Freescale Semiconductor, MPC8313ZQADDC Datasheet - Page 944

• Manufacturer Part Number: MPC8313ZQADDC
• Description: Microprocessors - MPU 8313 REV2.2 PB NO ENC
• Manufacturer: Freescale Semiconductor

Specifications of MPC8313ZQADDC

• Processor Series: MPC8313
• Core: e300
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 133 MHz
• Program Memory Size: 16 KB
• Data Ram Size: 16 KB
• Interface Type: I2C
• Mounting Style: SMD/SMT
• Package / Case: PBGA
• Number Of Programmable I/os: 32
• Number Of Timers: 4

Universal Serial Bus Interface
16-16
Bits
6
5
4
3
2
1
0
(USBERRINT)
(USBINT)
Name
URI
PCI
UEI
AAI
SEI
FRI
UI
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
USB reset received. This is a non-EHCI bit. When the USB DR controller detects a USB reset and
enters the default state, this bit will be set. Software can write a 1 to this bit to clear the USB reset
received status bit. Only used by the device mode.
0 No reset received
1 Reset received
Interrupt on async advance. System software can force the controller to issue an interrupt the next
time the USB DR controller advances the asynchronous schedule by writing a one to USBCMD[IAA].
This status bit indicates the assertion of that interrupt source. Only used by the host mode.
0 No async advance interrupt
1 Async advance interrupt
System error. This bit is set whenever an error is detected on the system bus. If USBINTR[SEE] is set,
an interrupt will be generated. The interrupt and status bits will remain asserted until cleared by writing
a 1 to this bit. Additionally, when in host mode, USBCMD[RS] is cleared, effectively disabling the USB
DR controller. For the USB DR controller in device mode, an interrupt is generated, but no other action
is taken.
0 Normal operation
1 Error
Frame list rollover. The controller sets this bit to a one when the frame list index rolls over from its
maximum value to zero. The exact value at which the rollover occurs depends on the frame list size.
For example. If the frame list size (as programmed in USBCMD[FS]) is 1024, FRINDEX rolls over
every time FRINDEX [1 3] toggles. Similarly, if the size is 512, the USB DR controller sets this bit to a
one every time FHINDEX [12] toggles. Only used by the host mode.
Host mode:
Device mode:
This bit is not EHCI compatible.
USB error interrupt (USBERRINT). When completion of a USB transaction results in an error
condition, this bit is set by the controller. This bit is set along with the UI, if the TD on which the error
interrupt occurred also had its interrupt on complete (IOC) bit set. See Section 4.15.1 in EHCI for a
complete list of host error interrupt conditions. Also see
information on device error matrix. For the USB DR controller in device mode, only resume signaling
is detected, all others are ignored.
0 No error
1 Error detected
USB interrupt (USBINT). This bit is set by the controller when the cause of an interrupt is a completion
of a USB transaction where the transfer descriptor (TD) has an interrupt on complete (IOC) bit set.
This bit is also set by the controller when a short packet is detected. A short packet is when the actual
number of bytes received was less than the expected number of bytes.
• Port change detect. The controller sets this bit when a connect status occurs on any port, a port
• The USB DR controller sets this bit when it enters the full or high-speed operational state. When
Table 16-11. USBSTS Register Field Descriptions (continued)
enable/disable change occurs, an over current change occurs, or PORTSC[FPR] is set as the result
of a J-K transition on the suspended port.
the it exits the full or high-speed operation states due to reset or suspend events, the notification
mechanisms are USBSTS[URI] and USBSTS[SLI], respectively.
Description
Table 16-91
in this chapter for more
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