MPC8313ZQADDC Freescale Semiconductor, MPC8313ZQADDC Datasheet - Page 44

• Manufacturer Part Number: MPC8313ZQADDC
• Description: Microprocessors - MPU 8313 REV2.2 PB NO ENC
• Manufacturer: Freescale Semiconductor

Specifications of MPC8313ZQADDC

• Processor Series: MPC8313
• Core: e300
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 133 MHz
• Program Memory Size: 16 KB
• Data Ram Size: 16 KB
• Interface Type: I2C
• Mounting Style: SMD/SMT
• Package / Case: PBGA
• Number Of Programmable I/os: 32
• Number Of Timers: 4

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xliv
UPM Read Access Data Sampling...................................................................................... 10-86
GPCM Relaxed Timing Write (XACS = 0, ACS = 10, SCY = 0, CSNT = 1,
GPCM Relaxed Timing Write (XACS = 0, ACS = 00, SCY = 1, CSNT = 1,
GPCM Read Followed by Read (TRLX = 0, EHTR = 0, Fastest Timing) ......................... 10-54
GPCM Read Followed by Write (TRLX = 0, EHTR = 1, One-Cycle Extended
External Termination of GPCM Access.............................................................................. 10-56
Local Bus to 8-bit FCM Device Interface........................................................................... 10-58
FCM Basic Page Read Timing (PGS = 1, CSCT = 0, CST = 0, CHT = 1,
FCM Buffer RAM Memory Map for Small-Page (512-byte page) NAND
FCM Buffer RAM Memory Map for Large-Page (2-Kbyte page) NAND
FCM ECC Calculation ........................................................................................................ 10-61
ECC Placement in NAND Flash Spare Regions in Relation to FMR[ECCM] .................. 10-62
FCM Instruction Sequencer Mechanism............................................................................. 10-63
Timing of FCM Command/Address and Write Data Cycles
Example of FCM Command and Address Timing with Minimum Delay Parameters
Example of FCM Command and Address Timing with Relaxed Parameters
FCM Delay Prior to Sampling LFRB State ........................................................................ 10-68
FCM Read Data Timing (for TRLX = 0, RST = 0, SCY = 1, CLKDIV = 4*N) ................ 10-68
FCM Read Data Timing with Extended Hold Time (for TRLX = 0, EHTR = 1,
FCM Buffer RAM Memory Map During Boot Loading .................................................... 10-71
User-Programmable Machine Functional Block Diagram.................................................. 10-72
RAM Array Indexing .......................................................................................................... 10-73
Memory Refresh Timer Request Block Diagram ............................................................... 10-74
UPM Clock Scheme for LCRR[CLKDIV] = 2................................................................... 10-78
UPM Clock Scheme for LCRR[CLKDIV] = 4 or 8 ........................................................... 10-78
RAM Array and Signal Generation .................................................................................... 10-78
RAM Word Fields ............................................................................................................... 10-79
LCSn Signal Selection ........................................................................................................ 10-82
LBS Signal Selection .......................................................................................................... 10-83
Effect of LUPWAIT Signal ................................................................................................. 10-87
Multiplexed Address/Data Bus for 26-Bit Addressing ....................................................... 10-88
TRLX = 1, CLKDIV = 4, 8) .......................................................................................... 10-53
TRLX = 1, CLKDIV = 4, 8) .......................................................................................... 10-53
Hold Time on Reads) ..................................................................................................... 10-55
RST = 1, SCY = 0, TRLX = 0, EHTR = 1).................................................................... 10-58
Flash Devices ................................................................................................................. 10-60
Flash Devices ................................................................................................................. 10-61
(for TRLX = 0, CHT = 0, CST = 1, SCY = 1, CLKDIV = 4*N)................................... 10-66
(for TRLX = 0, CHT = 0, CST = 0, SCY = 0, CLKDIV = 4*N)................................... 10-67
(for TRLX = 1, CHT = 0, CST = 1, SCY = 2, CLKDIV = 4*N)................................... 10-67
RST = 1, SCY = 1, CLKDIV = 4*N)............................................................................. 10-69
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
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