MPC8313ZQADDC Freescale Semiconductor, MPC8313ZQADDC Datasheet - Page 1177

• Manufacturer Part Number: MPC8313ZQADDC
• Description: Microprocessors - MPU 8313 REV2.2 PB NO ENC
• Manufacturer: Freescale Semiconductor

Specifications of MPC8313ZQADDC

• Processor Series: MPC8313
• Core: e300
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 133 MHz
• Program Memory Size: 16 KB
• Data Ram Size: 16 KB
• Interface Type: I2C
• Mounting Style: SMD/SMT
• Package / Case: PBGA
• Number Of Programmable I/os: 32
• Number Of Timers: 4

15.6.2.13, 15-155
15.6.4.1.1, 15-162
15.6.4.1.4, 15-164
15.6.5.2.1, 15-171
15.6.6, 15-171
15.6.6.2, 15-173
15.6.6.4.1, 15-175
15.6.6.4.2, 15,175
15.6.6.5, 15-176
15.6.7.3, 15-182
Freescale Semiconductor
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
In Table 15-152, in the ‘Parser error’ row, deleted the note at the end of the
description.
Added the following bullet:
• The GPI field offers the user the ability to interrupt the core upon matching a
Added the following two sentences to end of section:
A functional interrupt is provided via use of the general purpose interrupt (GPI)
bit in the filer table. When a property matches the value in the RQPROP entry at
this index, and REJ = 0 and AND = 0, the filer will set IEVENT[FGPI] when the
corresponding receive frame is written to memory. This allows the user to set up
a filer rule where the core will be interrupted upon the reception of ‘special’
frames.
If the timer is enabled (TMR_CTRL[TE] = 1), then the interrupt dedicated for
timer events (in addition to the usual receive, transmit and error interrupts) will be
asserted.
In the second paragraph, last sentence, changed to the folllowing:
As soon as the hardware consumes a BD (by writing it back to memory), RBPTRn
will advance and the free BD count will reflect the correct number of available
free BDs.
In the first paragraph, deleted the last sentence. In the second paragraph, first
sentence, changed to the following: ‘IEEE 1588 ... nodes to a master clock ... .’ In
the third paragraph, first sentence changed to the following: ‘The eTSEC includes
a new timer ... .’
In Figure 15-141, removed the Parser/Data Extraction Logic unit.
Deleted Section 15.6.6.4.1 and renumbered the following section.
Replaced the first paragraph with the following:
The eTSEC receive filer has been enhanced with the addition of a general-purpose
event bit. This event bit can be used in conjunction with filing table rules to
identify 1588 packets and indicate these packets by setting special timer status
register bits (TMR_STAT). Additionally, 1588 packets can be easily identified by
upper-layer software by using the filer to queue all PTP packets to one or more
predefined virtual queues. See Section 15.6.4.1.1, “Filing Rules,” for further
information.
Added to new sections, including figures and tables, as follows:
In Table 15-163, offset 4–7, bits 0–31, in the Description column, added the
following sentence: ‘For best performance, use 64-byte aligned receive buffer
pointer addresses’.
rule that causes a frame to be filed to memory. Once the last RxBD
corresponding to that frame is written to memory, the IEVENT[FGPI] event
will be asserted. This bit will be set regardless of any interrupt coalescing that
may be set.
Revision History
A-19