MPC8313ZQADDC Freescale Semiconductor, MPC8313ZQADDC Datasheet - Page 945

• Manufacturer Part Number: MPC8313ZQADDC
• Description: Microprocessors - MPU 8313 REV2.2 PB NO ENC
• Manufacturer: Freescale Semiconductor

Specifications of MPC8313ZQADDC

• Processor Series: MPC8313
• Core: e300
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 133 MHz
• Program Memory Size: 16 KB
• Data Ram Size: 16 KB
• Interface Type: I2C
• Mounting Style: SMD/SMT
• Package / Case: PBGA
• Number Of Programmable I/os: 32
• Number Of Timers: 4

16.3.2.3
The interrupts to software are enabled with this register. An interrupt is generated when a bit is set and the
corresponding interrupt is active. The USB status register (USBSTS) still shows interrupt sources even if
they are disabled by the USBINTR register, allowing polling of interrupt events by the software.
Freescale Semiconductor
Offset 0x2_3148
Reset
Reset
31–11
Bits
10
9
8
7
6
5
W
W
R
R
31
15
ULPIE
Name
SRE
URE
AAE
SLE
—
—
USB Interrupt Enable Register (USBINTR)
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
Reserved, should be cleared.
ULPI interrupt enable. An event completion to the viewport register sets the USBSTS[ULPII]. If the ULPI
enables ULPIE bit to be set, then the USBINT (USBSTS[UI]) will occur.
0 Disable
1 Enable
Reserved, should be cleared.
Sleep enable. This is a non-EHCI bit. When this bit is a one, and USBSTS[SLI] transitions, the USB DR
controller will issue an interrupt. The interrupt is acknowledged by software writing a one to USBSTS[SLI].
Only used in device mode.
0 Disable
1 Enable
SOF received enable. This is a non-EHCI bit. When this bit is a one, and USBSTS[SRI] is a one, the
controller will issue an interrupt. The interrupt is acknowledged by software clearing USBSTS[SRI].
0 Disable
1 Enable
USB reset enable. This is a non-EHCI bit. When this bit is a one, USBSTS[URI] is a one, the device
controller will issue an interrupt. The interrupt is acknowledged by software clearing USBSTS[URI] bit. Only
used in device mode.
0 Disable
1 Enable
Interrupt on async advance enable. When this bit is a one, and USBSTS[AAI] is a one, the controller will
issue an interrupt at the next interrupt threshold. The interrupt is acknowledged by software clearing
USBSTS[AAI]. Only used in host mode.
0 Disable
1 Enable
—
Table 16-12. USBINTR Register Field Descriptions
Figure 16-10. USB Interrupt Enable (USBINTR)
11
ULPIE
10
—
9
SLE
All zeros
All zeros
8
—
Description
SRE
7
URE
6
AAE
5
SEE
4
Universal Serial Bus Interface
FRE
3
PCE
Access: Read/Write
2
UEE
1
16-17
UE
16
0