MPC8313ZQADDC Freescale Semiconductor, MPC8313ZQADDC Datasheet - Page 224

• Manufacturer Part Number: MPC8313ZQADDC
• Description: Microprocessors - MPU 8313 REV2.2 PB NO ENC
• Manufacturer: Freescale Semiconductor

Specifications of MPC8313ZQADDC

• Processor Series: MPC8313
• Core: e300
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 133 MHz
• Program Memory Size: 16 KB
• Data Ram Size: 16 KB
• Interface Type: I2C
• Mounting Style: SMD/SMT
• Package / Case: PBGA
• Number Of Programmable I/os: 32
• Number Of Timers: 4

System Configuration
5.2.11
In addition to being accessible by the e300 processor, the IMMR memory window is accessible from
external interfaces. This allows external masters on the I/O ports to configure the device.
External masters do not need to know the location of the IMMR memory in the local address map. Rather,
they access this region of the local memory map through a window defined by a register in the interface’s
programming model that is accessible to the external master from its external memory map.
The PCI base address for accessing the local IMMR memory is selectable through the PCI internal
memory map register (PIMMR), at offset 0x10, described in
Address Registers (PIBARn).”
by running a PCI configuration cycle. Subsequent memory accesses by a PCI master to the PCI address
range indicated by PIMMR are translated to the local address indicated by the current setting of
IMMRBAR.
5.3
The following sections describe some general information and configuration options that affect system
behavior and performance.
5.3.1
Table 5-20
1
5-16
Offset (Hex)
0x0011C–0x
0x00130–0x
0x00150–0x
Depends on the reset configuration word high configuration values.
0x0010C
0x0012C
Memory
0x00100
0x00104
0x00108
0x00110
0x00114
0x00118
0x00128
0014C
001FC
00124
Local
System Configuration
shows the memory map for the system configuration registers.
Accessing Internal Memory from External Masters
System Configuration Register Memory Map
System general purpose register low (SGPRL)
System general purpose register high (SGPRH)
System part and revision ID register (SPRIDR)
Reserved
System priority configuration register (SPCR)
System I/O configuration register low (SICRL)
System I/O configuration register high (SICRH)
Reserved
DDR control driver register (DDRCDR)
DDR debug status register (DDRDSR)
Reserved
Reserved
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
Table 5-20. System Configuration Register Memory Map
When the device is a PCI agent, an external PCI master sets this register
Register
Section 13.3.2.12, “PCI Inbound Base
Access
R/W
R/W
R/W
R/W
R/W
R/W
—
—
—
—
R
R
0x0000_0000
0x80B0_0021
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0004_0000
0x3300_0000
Reset
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Freescale Semiconductor
1
Section/Page
5.3.2.1/5-17
5.3.2.2/5-17
5.3.2.3/5-18
5.3.2.4/5-18
5.3.2.5/5-21
5.3.2.6/5-23
5.3.2.8/5-27
5.3.2.9/5-29
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