MPC8313ZQADDC Freescale Semiconductor, MPC8313ZQADDC Datasheet - Page 489

• Manufacturer Part Number: MPC8313ZQADDC
• Description: Microprocessors - MPU 8313 REV2.2 PB NO ENC
• Manufacturer: Freescale Semiconductor

Specifications of MPC8313ZQADDC

• Processor Series: MPC8313
• Core: e300
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 133 MHz
• Program Memory Size: 16 KB
• Data Ram Size: 16 KB
• Interface Type: I2C
• Mounting Style: SMD/SMT
• Package / Case: PBGA
• Number Of Programmable I/os: 32
• Number Of Timers: 4

Each memory bank (chip select) can be assigned to any of these three types of machines through the
machine select bits of the base register for that bank (BR
match occurs, the corresponding machine (GPCM, FCM, or UPM) then takes ownership of the external
signals that control the access and maintains control until the transaction ends.
10.4.1
The following subsections describe the basic architecture of the eLBC.
10.4.1.1
The defined base addresses are written to the BR
written to the OR
compared with each bank. Addresses are decoded by comparing the 17 MSBs of the address, masked by
OR
bank, the attributes defined in the BR
match is found in more than one bank, the lowest-numbered bank handles the memory access (that is, bank
0 has priority over bank 1).
10.4.1.2
The local bus uses a multiplexed address/data bus. Therefore the eLBC must distinguish between address
and data phases, which take place on the same bus (LAD pins). The LALE signal, when asserted, signifies
an address phase during which the eLBC drives the memory address on the LAD pins. An external address
Freescale Semiconductor
n
[AM], with the base address for each bank (BR
Basic Architecture
Address and Address Space Checking
External Address Latch Enable Signal (LALE)
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
n
Bank Select
Comparator
registers. Each time a local bus access is requested, the internal transaction address is
Address
Figure 10-29. Basic Operation of Memory Controllers in the eLBC
MSEL
Field
32-bit Physical
RAM Address (A)
32-bit System
Address
Internal Memory Access Request Select
n
and OR
UPM A/B/C
n
for that bank are used to control the memory access. If a
n
registers, while the corresponding address masks are
n
[BA]). If a match is found on a memory controller
Signals Timing Generator
n
[MSEL]), as illustrated in
External Signals
FCM buffer
RAM
FCM
GPCM
Enhanced Local Bus Controller
Figure
10-29. If a bank
10-41