MPC8313ZQADDC Freescale Semiconductor, MPC8313ZQADDC Datasheet - Page 770

• Manufacturer Part Number: MPC8313ZQADDC
• Description: Microprocessors - MPU 8313 REV2.2 PB NO ENC
• Manufacturer: Freescale Semiconductor

Specifications of MPC8313ZQADDC

• Processor Series: MPC8313
• Core: e300
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 133 MHz
• Program Memory Size: 16 KB
• Data Ram Size: 16 KB
• Interface Type: I2C
• Mounting Style: SMD/SMT
• Package / Case: PBGA
• Number Of Programmable I/os: 32
• Number Of Timers: 4

Enhanced Three-Speed Ethernet Controllers
15.5.3.3.3
The RXIC register enables and configures the operational parameters for interrupt coalescing associated
with received frames.
Table 15-29
15-52
Offset eTSEC1:0x2_4310; eTSEC2:0x2_5310
Reset
Bits
Bits
25
26
27
28
29
30
31
0
1
2
W
R
ICEN ICCS —
0
Name
Name
RXF1 Receive frame event occurred on ring 1. Set by the eTSEC if IEVENT[RXF] was set in relation to receiving a
RXF2 Receive frame event occurred on ring 2. Set by the eTSEC if IEVENT[RXF] was set in relation to receiving a
RXF3 Receive frame event occurred on ring 3. Set by the eTSEC if IEVENT[RXF] was set in relation to receiving a
RXF4 Receive frame event occurred on ring 4. Set by the eTSEC if IEVENT[RXF] was set in relation to receiving a
RXF5 Receive frame event occurred on ring 5. Set by the eTSEC if IEVENT[RXF] was set in relation to receiving a
RXF6 Receive frame event occurred on ring 6. Set by the eTSEC if IEVENT[RXF] was set in relation to receiving a
RXF7 Receive frame event occurred on ring 7. Set by the eTSEC if IEVENT[RXF] was set in relation to receiving a
ICEN
ICCS Interrupt coalescing timer clock source.
—
describes the fields of the RXIC register.
1
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
Receive Interrupt Coalescing Register (RXIC)
frame to this ring.
frame to this ring.
frame to this ring.
frame to this ring.
frame to this ring.
frame to this ring.
frame to this ring.
Interrupt coalescing enable
0 Interrupt coalescing is disabled. Interrupts are raised as they are received.
1 Interrupt coalescing is enabled. If the eTSEC receive frame interrupt is enabled (IMASK[RXFEN] is set),
0 The coalescing timer advances count every 64 eTSEC Rx interface clocks (TSECn_GTX_CLK).
1 The coalescing timer advances count every 64 system clocks. This mode is recommended for FIFO
Reserved
2
an interrupt is raised when the threshold number of frames is reached (defined by RXIC[ICFT]) or when
the threshold timer expires (determined by RXIC[ICTT]).
operation.
3
Figure 15-24
Table 15-28. RSTAT Field Descriptions (continued)
ICFT
Figure 15-24. RXIC Register Definition
Table 15-29. RXIC Field Descriptions
describes the RXIC register.
10 11
—
All zeros
Description
Description
15 16
ICTT
Freescale Semiconductor
Access: Read/Write
31