MPC8313ZQADDC Freescale Semiconductor, MPC8313ZQADDC Datasheet - Page 192

• Manufacturer Part Number: MPC8313ZQADDC
• Description: Microprocessors - MPU 8313 REV2.2 PB NO ENC
• Manufacturer: Freescale Semiconductor

Specifications of MPC8313ZQADDC

• Processor Series: MPC8313
• Core: e300
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 133 MHz
• Program Memory Size: 16 KB
• Data Ram Size: 16 KB
• Interface Type: I2C
• Mounting Style: SMD/SMT
• Package / Case: PBGA
• Number Of Programmable I/os: 32
• Number Of Timers: 4

Reset, Clocking, and Initialization
I
from the I
are successfully loaded or the PORESET flow is restarted.
4.3.3.3
If the device is configured not to load the reset configuration words from NOR Flash, NAND Flash, or an
I
configuration input signals, CFG_RESET_SOURCE[0:3]. In this mode, the device is assumed to be a PCI
agent, and therefore only clock modes differ among the four options.
The reset configuration words are driven internally with the values shown in
Table 4-24
hard-coded reset configuration words options, as described in
Source.”
4-26
2
2
C bus error detection, the device will continuously attempt to reload the hard reset configuration words
C EEPROM, it can also be initialized with one of five hard-coded default options, selected by the reset
CFG_RESET_
RCWL Bits:
Meaning:
SOURCE
Field:
Value
1000
1001
1010
1011
1100
2
C bus. The device does not negate HRESET and remains in hard reset state until the HRCWs
defines the hard-coded reset configuration word high fields values. These values select
Default Reset Configuration Words
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
In this mode the device is also configured to accept PCI configuration cycles
when completing its reset sequence (In PCI function configuration register,
the CFG_LOCK bit is cleared). In addition, the inbound window size of the
PCI inbound window attribute registers (PIWARn[IWS]) is set to 0b010011,
defining 1-Mbyte (2
Function Configuration
LBC
controller
clock:
csb_clk
0 1:1
1 2:1
Table 4-23. Hard Coded Reset Configuration Word Low Fields Values
LBCM
0
0
0
0
0
0
DDR
controller
clock:
csb_clk
0 1:1
1 2:1
DDRCM
1
1
1
1
1
1
(19+1)
Register.”
) memory windows. See
—
Res
2–3
10
10
10
10
10
NOTE
csb_clk :
PCI_CLK
ratio
SPMF:1
SPMF
0100
0010
0101
0010
0101
4–7
Section 4.3.1.1, “Reset Configuration Word
Section 13.3.3.24, “PCI
Res
—
8
0
0
0
0
0
Table 4-23
Core clock:
csb_clk ratio
COREPLL
0000100
0000101
0000011
0000100
0000100
9–15
Freescale Semiconductor
and
Table
16–31
16’b0
16’b0
16’b0
16’b0
16’b0
Res
—
4-24.