MPC8313ZQADDC Freescale Semiconductor, MPC8313ZQADDC Datasheet - Page 503

• Manufacturer Part Number: MPC8313ZQADDC
• Description: Microprocessors - MPU 8313 REV2.2 PB NO ENC
• Manufacturer: Freescale Semiconductor

Specifications of MPC8313ZQADDC

• Processor Series: MPC8313
• Core: e300
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 133 MHz
• Program Memory Size: 16 KB
• Data Ram Size: 16 KB
• Interface Type: I2C
• Mounting Style: SMD/SMT
• Package / Case: PBGA
• Number Of Programmable I/os: 32
• Number Of Timers: 4

10.4.2.4
External access termination is supported by the GPCM using the asynchronous LGTA input signal, which
is synchronized and sampled internally by the local bus. If, during assertion of LCSn, the sampled LGTA
signal is asserted, it is converted to an internal generation of transfer acknowledge, which terminates the
current GPCM access (regardless of the setting of OR
bus cycle to be effective. Note that because LGTA is synchronized, bus termination occurs two cycles after
LGTA assertion, so in case of read cycle, the device still must drive data as long as LOE is asserted.
The user selects whether transfer acknowledge is generated internally or externally (LGTA) by
programming OR
transfer acknowledge generation), but it is the only means by which an access can be terminated if
OR
Freescale Semiconductor
n
[SETA] = 1. The timing of LGTA is illustrated by the example in
LBCTL
LCLK
LCS n
LALE
LCSy
LAD
LOE
TA
External Access Termination (LGTA)
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
A
Rd. Address
n
[SETA]. Asserting LGTA always terminates an access, even if OR
(TRLX = 0, EHTR = 1, One-Cycle Extended Hold Time on Reads)
Figure 10-42. GPCM Read Followed by Write
Latched Read Address
Read Data
Extended hold
n
[SETA]). LGTA should be asserted for at least one
Bus turnaround
Figure
Wr. Address
10-43.
Enhanced Local Bus Controller
n
[SETA] = 0 (internal
Wr. Address
Wr. Data
10-55