MPC8313ZQADDC Freescale Semiconductor, MPC8313ZQADDC Datasheet - Page 683

• Manufacturer Part Number: MPC8313ZQADDC
• Description: Microprocessors - MPU 8313 REV2.2 PB NO ENC
• Manufacturer: Freescale Semiconductor

Specifications of MPC8313ZQADDC

• Processor Series: MPC8313
• Core: e300
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 133 MHz
• Program Memory Size: 16 KB
• Data Ram Size: 16 KB
• Interface Type: I2C
• Mounting Style: SMD/SMT
• Package / Case: PBGA
• Number Of Programmable I/os: 32
• Number Of Timers: 4

Table 14-25
Freescale Semiconductor
The following bits are described for information only. They are not under direct user control.
The following bits are controlled through the MODE0 field of the descriptor header.
51–53
54–55
56–57
61–62
0–50
Bits
58
59
60
63
Name
SCM
ECM
RDK
CM
FM
IM
ED
—
—
describes AESUMR fields.
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
Reserved
Sub-cipher-mode. Specifies additional options specific to particular cipher modes.
Reserved, must be set to zero.
Extend cipher mode. Used in combination with bits 61–62 “Cipher Mode” to define the mode of AES
operation. See
Final MAC (FM). Processes final message block and generates final MAC tag at end of message processing
(CCM mode only)
0 Do not generate final MAC tag
1 Generate final MAC tag after CCM processing is complete.
Initialize MAC(IM). Initializes AESU for new message (CCM mode only)
0 Do not initialize (context will be loaded by host)
1 Initialize new message with nonce
Restore decrypt key (RDK). Specifies that key data write will contain pre-expanded key (decrypt mode only).
See note below on use of RDK bit.
0 Expand the user key prior to decrypting the first block
1 Do not expand the key. The expanded decryption key will be written following the context switch.
Cipher mode. Used in combination with bits 56–57 (Extend Cipher Mode) to define the mode of AES
operation. See
Encrypt/Decrypt. If set, AESU operates the encryption algorithm; if not set, AESU operates the decryption
algorithm.
0 Perform decryption
1 Perform encryption
Note: This bit is ignored if CM is set to ‘11’ (CTR mode).
• XOR cipher mode: specifies the number of sources to be XORed together. Valid values are 2 and 3.
• For all other cipher modes, this field must be 0.
CCM (without ICV comparison)
CCM with ICV comparison
Table 14-26
Table 14-26
Table 14-25. AESUMR Field Descriptions
Mode
SRT
ECB
CBC
CTR
Table 14-26. AES Cipher Modes
1
for mode bit combinations.
for mode bit combinations.
ECM (56–57)
Description
00
00
00
01
10
11
CM (61–62)
00
01
11
11
00
00
Security Engine (SEC) 2.2
14-41