MPC8313ZQADDC Freescale Semiconductor, MPC8313ZQADDC Datasheet - Page 610

• Manufacturer Part Number: MPC8313ZQADDC
• Description: Microprocessors - MPU 8313 REV2.2 PB NO ENC
• Manufacturer: Freescale Semiconductor

Specifications of MPC8313ZQADDC

• Processor Series: MPC8313
• Core: e300
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 133 MHz
• Program Memory Size: 16 KB
• Data Ram Size: 16 KB
• Interface Type: I2C
• Mounting Style: SMD/SMT
• Package / Case: PBGA
• Number Of Programmable I/os: 32
• Number Of Timers: 4

PCI Bus Interface
13.3.3.3
Figure 13-21
Table 13-25
13-28
Offset 04
Reset
W
15–11
R
Bits
10
9
8
7
6
5
4
3
2
1
0
15
shows the bit settings of the PCI command register.
PCI Command Configuration Register
SERREN
shows the PCI command fields.
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
PERRR
Name
BMST
INTD
MEM
FB-B
MWI
SC
I/O
—
—
—
Table 13-25. PCI Command Configuration Register Field Descriptions
—
Reserved
Interrupt Disable. Setting this bit masks the PCI_INTA output.
0 PCI_INTA provides the device interrupt status.
1 PCI_INTA is always negated.
Fast back-to-back. Hard-wired to 0.
if this bit and bit 6 are 1.
0 PCI_SERR is never asserted.
1 PCI_SERR may be asserted to indicate error conditions.
Reserved
0 Parity errors are ignored and normal operation continues.
1 Standard parity error treatment.
Reserved
Memory-write-and-invalidate. Hard-wired to 0.
Special cycles. Hard-wired to 0.
Bus master. Controls the PCI controller’s ability to be a master on the PCI bus. At reset, this bit is
cleared in Agent Mode and set in Host Mode.
0 The PCI controller does not generate PCI accesses.
1 The PCI controller behaves as a bus master.
Memory space. Controls the response to memory space accesses.
0 The PCI controller does not respond to Memory Space accesses.
1 The PCI controller as a target responds to Memory Space accesses.
I/O space. Hard-wired to 0.
SERR enable. This bit is an enable bit for the SERR driver. Address parity errors are reported only
Parity error response. Controls the PCI controller’s response to a parity error.
Figure 13-21. PCI Command Configuration Register
11
INTD
10
FB-B
9
SERREN
8
All zeros
—
7
Description
PERRR
6
—
5
MWI
4
SC
3
Freescale Semiconductor
BMST MEM
2
Access: Mixed
1
I/O
0