MPC8313ZQADDC Freescale Semiconductor, MPC8313ZQADDC Datasheet - Page 27

• Manufacturer Part Number: MPC8313ZQADDC
• Description: Microprocessors - MPU 8313 REV2.2 PB NO ENC
• Manufacturer: Freescale Semiconductor

Specifications of MPC8313ZQADDC

• Processor Series: MPC8313
• Core: e300
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 133 MHz
• Program Memory Size: 16 KB
• Data Ram Size: 16 KB
• Interface Type: I2C
• Mounting Style: SMD/SMT
• Package / Case: PBGA
• Number Of Programmable I/os: 32
• Number Of Timers: 4

Paragraph
Number
15.5.4.3.2
15.5.4.3.3
15.5.4.3.4
15.5.4.3.5
15.5.4.3.6
15.5.4.3.7
15.5.4.3.8
15.5.4.3.9
15.5.4.3.10
15.6
15.6.1
15.6.1.1
15.6.1.2
15.6.1.3
15.6.1.4
15.6.1.5
15.6.1.6
15.6.2
15.6.2.1
15.6.2.1.1
15.6.2.1.2
15.6.2.2
15.6.2.3
15.6.2.4
15.6.2.5
15.6.2.5.1
15.6.2.5.2
15.6.2.6
15.6.2.7
15.6.2.7.1
15.6.2.7.2
15.6.2.8
15.6.2.9
15.6.2.10
15.6.2.10.1
15.6.2.10.2
15.6.2.10.3
15.6.2.11
15.6.2.12
15.6.2.13
15.6.3
Freescale Semiconductor
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
Functional Description............................................................................................... 15-134
Connecting to Physical Interfaces on Ethernet ...................................................... 15-134
TCP/IP Off-Load ................................................................................................... 15-160
Gigabit Ethernet Controller Channel Operation ................................................... 15-143
Media-Independent Interface (MII) ................................................................... 15-135
Reduced Media-Independent Interface (RMII) ................................................. 15-135
Reduced Gigabit Media-Independent Interface (RGMII) ................................. 15-136
Reduced Ten-Bit Interface (RTBI) .................................................................... 15-137
Ethernet Physical Interfaces Signal Summary................................................... 15-139
SGMII Interface................................................................................................. 15-143
Initialization Sequence....................................................................................... 15-143
Soft Reset and Reconfiguring Procedure........................................................... 15-145
Gigabit Ethernet Frame Transmission ............................................................... 15-145
Gigabit Ethernet Frame Reception .................................................................... 15-147
Ethernet Preamble Customization ..................................................................... 15-148
RMON Support.................................................................................................. 15-150
Frame Recognition............................................................................................. 15-150
Magic Packet Mode ........................................................................................... 15-154
Flow Control...................................................................................................... 15-154
Interrupt Handling ............................................................................................. 15-155
Inter-Frame Gap Time ....................................................................................... 15-158
Internal and External Loop Back ....................................................................... 15-158
Error-Handling Procedure.................................................................................. 15-158
Status Register (SR)....................................................................................... 15-125
AN Advertisement Register (ANA) .............................................................. 15-126
AN Link Partner Base Page Ability Register (ANLPBPA)........................... 15-128
AN Expansion Register (ANEX) .................................................................. 15-129
AN Next Page Transmit Register (ANNPT).................................................. 15-130
AN Link Partner Ability Next Page Register (ANLPANP) .......................... 15-130
Extended Status Register (EXST) ................................................................. 15-131
Jitter Diagnostics Register (JD) ..................................................................... 15-132
TBI Control Register (TBICON)................................................................... 15-133
Hardware Controlled Initialization ................................................................ 15-144
User Initialization .......................................................................................... 15-144
User-Defined Preamble Transmission ........................................................... 15-148
User-Visible Preamble Reception.................................................................. 15-149
Destination Address Recognition and Frame Filtering ................................. 15-151
Hash Table Algorithm.................................................................................... 15-152
Interrupt Coalescing ...................................................................................... 15-156
Interrupt Coalescing By Frame Count Threshold.......................................... 15-156
Interrupt Coalescing By Timer Threshold ..................................................... 15-157
Contents
Title
Number
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