MPC8313ZQADDC Freescale Semiconductor, MPC8313ZQADDC Datasheet - Page 577

• Manufacturer Part Number: MPC8313ZQADDC
• Description: Microprocessors - MPU 8313 REV2.2 PB NO ENC
• Manufacturer: Freescale Semiconductor

Specifications of MPC8313ZQADDC

• Processor Series: MPC8313
• Core: e300
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 133 MHz
• Program Memory Size: 16 KB
• Data Ram Size: 16 KB
• Interface Type: I2C
• Mounting Style: SMD/SMT
• Package / Case: PBGA
• Number Of Programmable I/os: 32
• Number Of Timers: 4

In both modes, setting the start bit in the DMA mode register begins the DMA transfer.
The DMA controller supports unaligned transfers for both the source and destination addresses. It gathers
data beginning at the source address and aligns the data accordingly before sending it to the destination
address. The DMA controller assumes that the source and destination addresses are valid PCI or CSB
memory addresses.
Accesses to CSB memory depend on the alignment of the source and destination addresses and the size of
the transfer. The DMA controller transfers a full cache line whenever possible. Misaligned destination
addresses result in sub-transfers of less than a cache line on the initial and final beats of the transfer;
intermediate beats transfer full cache lines. Configuring a DMA channel for address hold mode DMAMRn
precludes cache line transfers.
PCI memory read operations depend on the PRC (PCI read command) field in the mode register, the
alignment of the source address, and the size of the transfer. The DMA controller attempts to read a full
cache line whenever possible. Writing to PCI memory depends on the alignment of the destination address
and the size of the transfer.
12.4.3.1
The four DMA channels use up to four cache lines (128 bytes) of buffer space in the IOS in addition to
16 bytes of local buffer space. Because no address snooping occurs in these internal queues, data posted
in these queues is not visible to the rest of the system while a DMA transfer is in progress. It is the
responsibility of application software to ensure the coherency of the region being transferred during the
DMA process.
Snooping of the CPU or processor data cache is selectable during DMA transactions. A snoop bit is
provided in the DMA current descriptor address register (DMACDARn) and the DMA next descriptor
address register (DMANDARn) that allows software to control when the cache is snooped on a per
segment basis.
12.4.3.2
DMA transfers are halted either by clearing the CS (channel start) bit in the DMA mode register
(DMAMRn) or when encountering an error condition. In either case, the application software can do one
of the following:
Freescale Semiconductor
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•
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transfer finishes after all the bytes specified in the byte count register have been transferred. See
Section 12.5.1, “Initialization Steps in Direct Mode,”
Chaining mode, in chaining mode, the DMA controller loads descriptors from memory prior to a
DMA transfer. The DMA controller begins the transfer according to the descriptor information
loaded for each segment. Once the current segment is finished, the DMA controller reads the next
descriptor from memory and begins another DMA transfer. The process is finished if the current
descriptor is the last one in the chain. See
for more details on initialization steps.
Continue the DMA transfer
Reconfigure the DMA for a new transfer
DMA Coherency
Halt and Error Conditions
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
Section 12.5.2, “Initialization Steps in Chaining Mode,”
for more details on initialization steps.
DMA/Messaging Unit
12-17