MPC8313ZQADDC Freescale Semiconductor, MPC8313ZQADDC Datasheet - Page 958

• Manufacturer Part Number: MPC8313ZQADDC
• Description: Microprocessors - MPU 8313 REV2.2 PB NO ENC
• Manufacturer: Freescale Semiconductor

Specifications of MPC8313ZQADDC

• Processor Series: MPC8313
• Core: e300
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 133 MHz
• Program Memory Size: 16 KB
• Data Ram Size: 16 KB
• Interface Type: I2C
• Mounting Style: SMD/SMT
• Package / Case: PBGA
• Number Of Programmable I/os: 32
• Number Of Timers: 4

Universal Serial Bus Interface
16-30
Bits
5
4
3
2
Name
OCC
OCA
PEC
PE
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
Over-current change. This bit gets set when there is a change to over-current active. Software clears this bit
by writing a one to this bit position.
Host/OTG mode:
Device mode:
1 Over current detect.
0 No over current.
Over-current active. This bit will automatically transition from one to zero when the over current condition is
removed.
Host/OTG mode:
Device mode:
1 Port currently in over-current condition.
0 Port not in over-current condition.
Port enable/disable change.
For the root hub, this bit gets set only when a port is disabled due to disconnect on the port or due to the
appropriate conditions existing at the EOF2 point (See Chapter 11 of the USB Specification). Software clears
this by writing a one to it.[
In device mode:
1 Port disabled.
0 No change.
This field is zero if Port Power(PP) is zero.
Port enabled/disabled.
Host mode:
Device mode:
• The user can provide over-current detection to the USB n _PWRFAULT signal for this condition.
• This bit must always be 0.
• The user can provide over-current detection to the USB n _PWRFAULT signal for this condition.
• This bit must always be 0.
• The device port is always enabled. (This bit will be zero.)
• Ports can only be enabled by the controller as a part of the reset and enable. Software cannot enable a port
• When the port is disabled, (0) downstream propagation of data is blocked except for reset.
• This field is zero if Port Power(PP) is zero in host mode.
• The device port is always enabled. (This bit will be one.)
by writing a one to this field. Ports can be disabled by either a fault condition (disconnect event or other fault
condition) or by the host software. Note that the bit status does not change until the port state actually
changes. There may be a delay in disabling or enabling a port due to other host and bus events.
Table 16-23. PORTSC Register Field Descriptions (continued)
Description
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