MPC8313ZQADDC Freescale Semiconductor, MPC8313ZQADDC Datasheet - Page 388

• Manufacturer Part Number: MPC8313ZQADDC
• Description: Microprocessors - MPU 8313 REV2.2 PB NO ENC
• Manufacturer: Freescale Semiconductor

Specifications of MPC8313ZQADDC

• Processor Series: MPC8313
• Core: e300
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 133 MHz
• Program Memory Size: 16 KB
• Data Ram Size: 16 KB
• Interface Type: I2C
• Mounting Style: SMD/SMT
• Package / Case: PBGA
• Number Of Programmable I/os: 32
• Number Of Timers: 4

Integrated Programmable Interrupt Controller (IPIC)
All interrupt sources are prioritized and bits are set in the system interrupt pending register (SIPNR,
SEPNR) as interrupts occur regardless of whether they are masked in the IPIC. The prioritization of the
interrupt sources is flexible within the following groups:
The SIVCR is updated with a 7-bit vector corresponding to the sub-block with the highest current priority.
8.6.3
The relative priority in each internal group is programmable and can be changed dynamically. The group
priorities are programmed in the IPIC internal interrupt priority registers (SIPRRx) and can be changed
dynamically to implement a rotating priority.
In addition, the grouping of the locations of the interrupt entries has the following two options:
8.6.4
The relative priority between up to four internal and four external interrupts in each group is programmable
and can be changed dynamically. The group priorities are programmed in the IPIC mixed interrupt priority
registers (SMPRRx) and can be changed dynamically to implement a rotating priority.
In addition, the grouping of the locations of the mixed interrupt entries has the following two options:
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The relative priority of the eTSEC1 Tx, eTSEC1 Rx, eTSEC1 Err, eTSEC2 TX, eTSEC2 Rx and
USB DR internal interrupt signals can be modified.
The relative priority of the UART1, UART2, SPI, I2C1, I2C2, eTSEC1 1588 timer, eTSEC2 1588
timer, and SEC internal interrupt signals can be modified.
The relative priority of the IRQ0, IRQ1, IRQ2, and IRQ3 external interrupts, and RTC SECand PCI
internal interrupts can be modified.
The relative priority of the IRQ4 external interrupts, and RTC ALR, MU, SBA, and DMA internal
interrupts can be modified.
One interrupt source can be assigned to be the programmable highest priority.
Grouped. In the group scheme, all interrupts are grouped together at the top of
of most other interrupt sources. This scheme is ideal for applications where all interrupt sources
function at a very high data rate and interrupt latency is very important.
Spread. In the spread scheme, priorities are spread over
interrupt latencies. This scheme is also programmed but cannot be changed dynamically.
Grouped. In the group scheme, all interrupts are grouped together at the top of the priority table,
ahead of most other interrupt sources. See
for applications where all interrupt sources function at a very high data rate and interrupt latency
is very important.
Spread. In the spread scheme, priorities are spread over the table so other sources can have lower
interrupt latencies. This scheme is also programmed but cannot be changed dynamically.
Internal Interrupts Group Relative Priority
Mixed Interrupts Group Relative Priority
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
Table 8-31
for more information. This scheme is ideal
Table 8-31
so other sources can have lower
Freescale Semiconductor
Table
8-31, ahead