MPC8313ZQADDC Freescale Semiconductor, MPC8313ZQADDC Datasheet - Page 798

• Manufacturer Part Number: MPC8313ZQADDC
• Description: Microprocessors - MPU 8313 REV2.2 PB NO ENC
• Manufacturer: Freescale Semiconductor

Specifications of MPC8313ZQADDC

• Processor Series: MPC8313
• Core: e300
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 133 MHz
• Program Memory Size: 16 KB
• Data Ram Size: 16 KB
• Interface Type: I2C
• Mounting Style: SMD/SMT
• Package / Case: PBGA
• Number Of Programmable I/os: 32
• Number Of Timers: 4

Enhanced Three-Speed Ethernet Controllers
An interrupt can be generated upon any one counter’s rollover condition through a carry interrupt output
from the RMON. Each counter’s rollover condition can be discretely masked from causing an interrupt by
internal masking registers. In addition, each individual counter value may be reset on read access, or all
counters may be simultaneously reset by setting ECNTRL[CLRCNT].
The majority of MIB counters are Ethernet-specific.
15.5.3.6.1
Figure 15-52
Table 15-56
15.5.3.6.2
Figure 15-53
15-80
10–31
Bits
0–9
Offset eTSEC1:0x2_4680; eTSEC2:0x2_5680
Reset
Offset eTSEC1:0x2_4684; eTSEC2:0x2_5684
Reset
W
W
R
R
Name
TR64 Transmit and receive 64-byte frame counter—Increment for each good or bad frame transmitted and received
0
0
—
describes the fields of the TR64 register.
describes the definition for the TR64 register.
describes the definition for the TR127 register.
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
Figure 15-53. Transmit and Receive 65- to 127-Byte Frame Register Definition
Reserved
which is 64 bytes in length, inclusive (excluding preamble and SFD but including FCS bytes).
RMON counters do not comprehend custom VLAN tagged frames.
Affected counters include TRMGV, RMCA, RBCA, RXCF, RXPF, RXUO,
RALN, RFLR, ROVR, RJBR, TMCA, TBCA, TXPF, TXCF. Specifically,
custom VLAN tagged frames are not afforded the ability to be greater than
1518, as compared to the IEEE standard tagged frames.
Transmit and Receive 64-Byte Frame Counter (TR64)
Transmit and Receive 65- to 127-Byte Frame Counter (TR127)
Figure 15-52. Transmit and Receive 64-Byte Frame Register Definition
—
—
Table 15-56. TR64 Field Descriptions
9
9
10
10
NOTE
All zeros
All zeros
Description
TR64
TR127
Freescale Semiconductor
Access: Read/Write
Access: Read/Write
31
31