MPC8313ZQADDC Freescale Semiconductor, MPC8313ZQADDC Datasheet - Page 1077

• Manufacturer Part Number: MPC8313ZQADDC
• Description: Microprocessors - MPU 8313 REV2.2 PB NO ENC
• Manufacturer: Freescale Semiconductor

Specifications of MPC8313ZQADDC

• Processor Series: MPC8313
• Core: e300
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 133 MHz
• Program Memory Size: 16 KB
• Data Ram Size: 16 KB
• Interface Type: I2C
• Mounting Style: SMD/SMT
• Package / Case: PBGA
• Number Of Programmable I/os: 32
• Number Of Timers: 4

data structures and operational models that exist in the EHCI specification to support full and low speed
devices.
16.9.1.1
The following additions have been added to the capability registers to support the embedded transaction
translator Function:
See
16.9.1.2
The following additions have been added to the operational registers to support the embedded TT:
16.9.1.3
In a standard EHCI controller design, the EHCI host controller driver detects a Full speed (FS) or Low
speed (LS) device by noting if the port enable bit is set after the port reset operation. The port enable will
only be set in a standard EHCI controller implementation after the port reset operation and when the host
and device negotiate a High-Speed connection (that is, Chirp completes successfully).
The module will always set the port enable after the port reset operation regardless of the result of the host
device chirp result and the resulting port speed will be indicated by the PSPD field in PORTSC. Therefore,
the standard EHCI host controller driver requires an alteration to handle directly connected Full and Low
speed devices or hubs. The change is a fundamental one in that is summarized in
Freescale Semiconductor
After port enable bit is set following a connection and
reset sequence, the device/hub is assumed to be HS.
FS and LS devices are assumed to be downstream
from a HS hub thus, all port-level control is performed
through the Hub Class to the nearest Hub.
FS and LS devices are assumed to be downstream
from a HS hub with HubAddr=X. [where HubAddr > 0
and HubAddr is the address of the Hub where the bus
transitions from HS to FS/LS (that is, Split target hub)]
•
•
•
•
Section 16.3.1.3, “Host Controller Structural Parameters (HCSPARAMS),”
N_TT added to HSCPARAMS—Host Controller Structural Parameters
N_PTT added to HSCPARAMS—Host Controller Structural Parameters
ASYNCTTSTS is a new register.
Addition of two-bit Port Speed (PSPD) to the PORTSC register.
Table 16-96. Functional Differences Between EHCI and EHCI with Embedded TT
Capability Registers
Operational Registers
Discovery
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
Standard EHCI
After port enable bit is set following a connection and reset sequence,
the device/hub speed is noted from PORTSC.
FS and LS device can be either downstream from a HS hub or directly
attached. When the FS/LS device is downstream from a HS hub, then
port-level control is done using the Hub Class through the nearest Hub.
When a FS/LS device is directly attached, then port-level control is
accomplished using PORTSC.
FS and LS device can be either downstream from a HS hub with
HubAddr = X [HubAddr > 0] or directly attached [where HubAddr = 0 and
HubAddr is the address of the Root Hub where the bus transitions from
HS to FS/LS (that is, Split target hub is the root hub)]
EHCI with Embedded Transaction Translator
for usage information.
Table
Universal Serial Bus Interface
16-96.
16-149