MPC8313ZQADDC Freescale Semiconductor, MPC8313ZQADDC Datasheet - Page 306

• Manufacturer Part Number: MPC8313ZQADDC
• Description: Microprocessors - MPU 8313 REV2.2 PB NO ENC
• Manufacturer: Freescale Semiconductor

Specifications of MPC8313ZQADDC

• Processor Series: MPC8313
• Core: e300
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 133 MHz
• Program Memory Size: 16 KB
• Data Ram Size: 16 KB
• Interface Type: I2C
• Mounting Style: SMD/SMT
• Package / Case: PBGA
• Number Of Programmable I/os: 32
• Number Of Timers: 4

Arbiter and Bus Monitor
6.2.2
The arbiter timers register (ATR) defines the arbiter address time out (ATO) and data time out (DTO)
values.
Table 6-3
6-4
26–27
28–31
16–31
0–15
Bits
Bits
Offset 0x04
Reset 1
W
R
Figure 6-2
Name
DTO
ATO
0
describes ATR fields.
PARKM
APARK
Name
Arbiter Timers Register (ATR)
1
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
1
Data time out. Specifies the time-out period for the data tenure. The granularity of this field is bus clocks. The
maximum value is coherent system bus clocks. Data time_out occurs if the data tenure does not end before
the specified time-out period. When DTO = n, the timeout cycle is n*128.
0000 Reserved
0001 128 clock cycles
0002 256 clock cycles
0003 384 clock cycles
...
FFFF 8355840 clock cycles
Address time out. Specifies the time-out period for the address tenure. The granularity of this field is bus
clocks. Maximum value is coherent system bus clocks. Address time-out occurs if the address tenure did not
end before the specified time-out period. When ATO = n, the timeout cycle is n*128.
0000 Reserved
0001 128 clock cycles
0002 256 clock cycles
0003 384 clock cycles
...
FFFF 8355840 clock cycles
1
shows the fields of ATR.
Address parking. Specifies arbiter bus parking mode.
00 Park to master. Arbiter parks the address bus to the master, that is selected by numeric value of
01 Park to last owner. Arbiter parks the address bus to last bus owner.
10 Disable. Arbiter does not assert BG to any master, if no BR is present.
11 Reserved
Parking master.
0000 e300 core
0001 PCI, DMA
0010 TSEC1, TSEC2
0011 Encryption core
0100 USB
0101–1111Reserved
1
PARKM field.
1
1
Table 6-2. ACR Field Descriptions (continued)
1
DTO
Figure 6-2. Arbiter Timers Register (ATR)
1
Table 6-3. ATR Field Descriptions
1
1
1
1
1
1
15 16
1
Description
1
Description
1
1
1
1
1
1
1
ATO
1
Freescale Semiconductor
Access: User read/write
1
1
1
1
1
1
31
1