MPC8313ZQADDC Freescale Semiconductor, MPC8313ZQADDC Datasheet - Page 525

• Manufacturer Part Number: MPC8313ZQADDC
• Description: Microprocessors - MPU 8313 REV2.2 PB NO ENC
• Manufacturer: Freescale Semiconductor

Specifications of MPC8313ZQADDC

• Processor Series: MPC8313
• Core: e300
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 133 MHz
• Program Memory Size: 16 KB
• Data Ram Size: 16 KB
• Interface Type: I2C
• Mounting Style: SMD/SMT
• Package / Case: PBGA
• Number Of Programmable I/os: 32
• Number Of Timers: 4

10.4.4.2.2
RAM array contents may also be read for debug purposes, for example, by alternating dummy read
transactions, each time followed by reads of MDR (M
illustrates the steps required to perform two reads from the RAM array at non-sequential addresses
assuming that the relevant BR
10.4.4.3
RAM word fields specify the value of the various external signals at a granularity of up to four values for
each bus clock cycle. The signal timing generator causes external signals to behave according to timing
specified in the current RAM word. For LCRR[CLKDIV] = 4 or 8, each bit in the RAM word relating to
LCSn and LBS timing specifies the value of the corresponding external signal at each quarter phase of the
bus clock. If LCRR[CLKDIV] = 2, the external signal can change value only on each half phase of the bus
clock. If the RAM word in this case (LCRR[CLKDIV] = 2) specifies a quarter phase signal change, the
signal timing generator interprets this as a half cycle change.
The division of UPM bus cycles into phases is shown in
LCRR[CLKDIV] = 2, the bus cycle comprises only two active phases, T1 and T3, which correspond with
the first and second halves of the bus clock cycle, respectively. However, if LCRR[CLKDIV] = 4 or 8, four
phases, T1–T4, define four quarters of the bus clock cycle. Because T2 and T4 are inactive when
LCRR[CLKDIV] = 2, UPM ignores signal timing programmed for assertion in either of these phases in
the case LCRR[CLKDIV] = 2.
Freescale Semiconductor
1. Program M
2. Read M
3. Perform a dummy read transaction.
4. Read/check M
5. Read MDR.
6. Program M
7. Read M
8. Perform a dummy read transaction.
9. Read/check M
10. Read MDR.
such as RAM array address.
proceed to step 5. Repeat step 4 until incremented.
such as RAM array address.
proceed to step 10. Repeat step 9 until incremented.
UPM Signal Timing
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
UPM Programming Example (Two Sequential Reads from the RAM Array)
x
x
MR to ensure that the M
MR to ensure that the M
x
x
MR for the first read with the desired RAM array address.
MR for the second read with the desired RAM array address.
x
x
MR[MAD]. If incremented, the previous dummy read transaction is completed;
MR[MAD]. If incremented, the previous dummy read transaction is completed;
n
and OR
n
x
x
registers have been previously set up:
MR has already been updated with the desired configuration,
MR has already been updated with the desired configuration,
x
MR[OP] = 0b10). The following example further
Figure 10-61
and
Figure
Enhanced Local Bus Controller
10-62. If
10-77