MPC8313ZQADDC Freescale Semiconductor, MPC8313ZQADDC Datasheet - Page 24

• Manufacturer Part Number: MPC8313ZQADDC
• Description: Microprocessors - MPU 8313 REV2.2 PB NO ENC
• Manufacturer: Freescale Semiconductor

Specifications of MPC8313ZQADDC

• Processor Series: MPC8313
• Core: e300
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 133 MHz
• Program Memory Size: 16 KB
• Data Ram Size: 16 KB
• Interface Type: I2C
• Mounting Style: SMD/SMT
• Package / Case: PBGA
• Number Of Programmable I/os: 32
• Number Of Timers: 4

Paragraph
Number
15.5.3.3
15.5.3.3.1
15.5.3.3.2
15.5.3.3.3
15.5.3.3.4
15.5.3.3.5
15.5.3.3.6
15.5.3.3.7
15.5.3.3.8
15.5.3.3.9
15.5.3.3.10
15.5.3.3.11
15.5.3.3.12
15.5.3.3.13
15.5.3.4
15.5.3.4.1
15.5.3.4.2
15.5.3.4.3
15.5.3.4.4
15.5.3.4.5
15.5.3.5
15.5.3.5.1
15.5.3.5.2
15.5.3.5.3
15.5.3.5.4
15.5.3.5.5
15.5.3.5.6
15.5.3.5.7
15.5.3.5.8
15.5.3.5.9
15.5.3.5.10
15.5.3.5.11
15.5.3.5.12
15.5.3.5.13
15.5.3.5.14
15.5.3.5.15
15.5.3.5.16
15.5.3.6
15.5.3.6.1
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MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
eTSEC Receive Control and Status Registers ..................................................... 15-48
MAC Functionality.............................................................................................. 15-64
MAC Registers .................................................................................................... 15-67
MIB Registers...................................................................................................... 15-79
Receive Control Register (RCTRL) ................................................................ 15-48
Receive Status Register (RSTAT).................................................................... 15-50
Receive Interrupt Coalescing Register (RXIC) ............................................... 15-52
Receive Queue Control Register (RQUEUE) ................................................. 15-53
Receive Bit Field Extract Control Register (RBIFX)...................................... 15-54
Receive Queue Filer Table Address Register (RQFAR) ................................. 15-55
Receive Queue Filer Table Control Register (RQFCR) .................................. 15-56
Receive Queue Filer Table Property Register (RQFPR) ................................. 15-57
Maximum Receive Buffer Length Register (MRBLR) ................................... 15-61
Receive Data Buffer Pointer High Register (RBDBPH) ................................. 15-62
Receive Buffer Descriptor Pointers 0–7 (RBPTR0–RBPTR7) ....................... 15-62
Receive Descriptor Base Address Registers (RBASE0–RBASE7) ................ 15-63
Receive Stamp Register (TMR_RXTS_H/L).................................................. 15-63
Configuring the MAC ..................................................................................... 15-64
Controlling CSMA/CD.................................................................................... 15-64
Handling Packet Collisions ............................................................................ 15-65
Controlling Packet Flow.................................................................................. 15-65
Controlling PHY Links.................................................................................... 15-66
MAC Configuration 1 Register (MACCFG1)................................................. 15-67
MAC Configuration 2 Register (MACCFG2)................................................. 15-68
Inter-Packet Gap/Inter-Frame Gap Register (IPGIFG) ................................... 15-70
Half-Duplex Register (HAFDUP) ................................................................... 15-71
Maximum Frame Length Register (MAXFRM) ............................................. 15-72
MII Management Configuration Register (MIIMCFG) .................................. 15-72
MII Management Command Register (MIIMCOM)....................................... 15-73
MII Management Address Register (MIIMADD)........................................... 15-74
MII Management Control Register (MIIMCON)............................................ 15-75
MII Management Status Register (MIIMSTAT) ............................................. 15-75
MII Management Indicator Register (MIIMIND)........................................... 15-76
Interface Status Register (IFSTAT).................................................................. 15-76
MAC Station Address Part 1 Register (MACSTNADDR1) ........................... 15-77
MAC Station Address Part 2 Register (MACSTNADDR2) ........................... 15-78
MAC Exact Match Address 1–15 Part 1 Registers
MAC Exact Match Address 1–15 Part 2 Registers
Transmit and Receive 64-Byte Frame Counter (TR64) .................................. 15-80
(MAC01ADDR1–MAC15ADDR1)............................................................ 15-78
(MAC01ADDR2–MAC15ADDR2)............................................................ 15-79
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