MPC8313ZQADDC Freescale Semiconductor, MPC8313ZQADDC Datasheet - Page 175

• Manufacturer Part Number: MPC8313ZQADDC
• Description: Microprocessors - MPU 8313 REV2.2 PB NO ENC
• Manufacturer: Freescale Semiconductor

Specifications of MPC8313ZQADDC

• Processor Series: MPC8313
• Core: e300
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 133 MHz
• Program Memory Size: 16 KB
• Data Ram Size: 16 KB
• Interface Type: I2C
• Mounting Style: SMD/SMT
• Package / Case: PBGA
• Number Of Programmable I/os: 32
• Number Of Timers: 4

Figure 4-2
4.2.4
The SRESET signal can be initiated externally by asserting SRESET. SRESET assertion asserts the sreset
input to the e300 core. No other hardware is reset.
4.3
The device is initialized using two complementary methods, latching CFG_RESET_SOURCE and
loading the reset configuration words. Initially, a few input signals are sampled during the assertion of the
PORESET signal. These signals determine whether a reset configuration word is required and the device
source interface from which it is loaded. According to the value on these signals, the device continues
loading the reset configuration word.
4.3.1
Reset configuration input signals are on device pins that have other functions when the device is not in
reset state. These input signals are sampled into registers during the assertion of PORESET, after a stable
clock is supplied (PCI_CLK), and must be pulled high or low by external resistors as long as HRESET is
asserted. While the PORESET and HRESET signals are asserted, all other signal drivers connected to
these signals must be in the high-impedance state. Refer to the hardware specifications for proper resistor
values for pulling reset configuration signals high or low.
Freescale Semiconductor
PCI_CLK/PCI_SYNC_IN
CLKIN (Host Mode) or
Reset Configuration
Reset Configuration
Reset Configuration
(Input or Output)
shows a timing diagram of the hard reset flow.
Words Loading
Soft Reset Flow
Reset Configuration Signals
(Agent Mode)
Input Signals
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
PORESET
HRESET
(Input)
(Input)
TRST
Figure 4-2. Hard Reset Flow
configuration words
Start loading reset
Stable clock
Reset, Clocking, and Initialization
Duration depends on
configuration words.
End loading reset
source
4-9