MPC8313ZQADDC Freescale Semiconductor, MPC8313ZQADDC Datasheet - Page 1212

• Manufacturer Part Number: MPC8313ZQADDC
• Description: Microprocessors - MPU 8313 REV2.2 PB NO ENC
• Manufacturer: Freescale Semiconductor

Specifications of MPC8313ZQADDC

• Processor Series: MPC8313
• Core: e300
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 133 MHz
• Program Memory Size: 16 KB
• Data Ram Size: 16 KB
• Interface Type: I2C
• Mounting Style: SMD/SMT
• Package / Case: PBGA
• Number Of Programmable I/os: 32
• Number Of Timers: 4

T–U
System management interrupt (smi), 7-34
System timers
T
TA (LBC data transfer acknowledge) signal, 10-43
TAP (test access port) controller, 20-4
TBL/TBU (time base facility)
True little-endian, 7-24
TSEC
TSECn_COL (eTSEC 1–4 collision input) signals, 15-8
TSECn_CRS (eTSEC 1–4 carrier sense input/FIFO receiver
TSECn_GTX_CLK (eTSEC 1–4 gigabit transmit clock)
TSECn_RX_CLK (eTSEC 1–4 receive clock) signals, 15-9
TSECn_RX_DV (eTSEC 1–4 receive data valid) signals,
TSECn_RX_ER (eTSEC 1–4 receive error) signals, 15-10
TSECn_RXD[7:0] (eTSEC 1–4 receive data in) signals, 15-9
TSECn_TX_CLK (eTSEC 1–4 transmit clock in) signals,
TSECn_TX_EN (eTSEC 1–4 transmit data valid) signals,
TSECn_TX_ER (eTSEC 1–4 transmit error) signals, 15-10
TSECn_TXD[7:0] (eTSEC 1–4 transmit data out) signals,
U
Universal serial bus, see USB interface
UPWAIT (LBC UPM wait) signal, 10-6, 10-73
USB interface
Index-14
overview, 1-18
for reading, 7-17
time base/decrementer, 7-11
overview, 1-11
asynchronous schedule, 16-47, 16-80
dual-role controller
features, 16-2
frame list
functional descriptions
flow control) signals, 15-8
signals, 15-8
15-9
15-10
15-10
15-10
adding queue heads, 16-81
empty detection, 16-84
list queue head pointer, 16-49
organization, 16-49
reclamation status bit, 16-85
removing queue heads, 16-82
traversal (start event), 16-85
overview, 1-14
link pointer format, 16-48
DMA engine, 16-46
MPC8313E PowerQUICC™ II Pro Integrated Processor Reference Manual, Rev. 2
host data structures, 16-47
host operations, 16-67
isochronous (high-speed) transfer descriptor (iTD), 16-47,
memory map/register definitions, 16-5
modes of operation, 16-3
module, 16-2
modules
overview, 1-13, 16-2
periodic frame list, 16-47
periodic frame span traversal node (FSTN), 16-66
periodic schedule, 16-47
queue element transfer descriptor (qTD), 16-47, 16-56
FIFO RAM controller, 16-46
PHY interface, 16-46
system interface, 16-45
behavior during wake-up events, 16-71
host controller initialization, 16-68
periodic schedule, 16-75
periodic schedule frame boundaries vs. bus frame
port power control (PPC), 16-69
port suspend/resume, 16-70
reporting over-current, 16-69
schedule traversal rules, 16-71
split transactions, 16-90
suspend/resume, 16-69
buffer page pointer list (plus), 16-51
host controller operational model, 16-76
managing transfers, 16-76
next link pointer, 16-50
periodic scheduling threshold, 16-79
software operational model, 16-78
transaction status and control list, 16-51
dual-role (DR), 16-2
back path link pointer, 16-67
normal path pointer, 16-67
organization, 16-48
rebalancing, 16-104
alternate next pointer, 16-57
buffer page pointer list, 16-61
next pointer, 16-57
token, 16-58
execution state machine for isochronous, 16-110
isochronous, 16-104
periodic interrupt—Do-Complete-Split, 16-100
periodic interrupt—Do-Start-Split, 16-99
scheduling mechanisms for isochronous, 16-105
see also USB interface, split transactions
tests for execution, 16-100
tracking progress for isochronous transfers, 16-108
16-49
boundaries, 16-72
Freescale Semiconductor
Index