MPC8313ZQADDC Freescale Semiconductor, MPC8313ZQADDC Datasheet - Page 371

• Manufacturer Part Number: MPC8313ZQADDC
• Description: Microprocessors - MPU 8313 REV2.2 PB NO ENC
• Manufacturer: Freescale Semiconductor

Specifications of MPC8313ZQADDC

• Processor Series: MPC8313
• Core: e300
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 133 MHz
• Program Memory Size: 16 KB
• Data Ram Size: 16 KB
• Interface Type: I2C
• Mounting Style: SMD/SMT
• Package / Case: PBGA
• Number Of Programmable I/os: 32
• Number Of Timers: 4

Table 8-10
8.5.4
SIPRR_A, shown in
receive request (TSEC1 Rx), TSEC1 transmit/receive error (TSEC1 Err), TSEC2 transmit request (TSEC2
Tx), TSEC2 receive request (TSEC2 Rx) TSEC2 transmit/receive error (TSEC2 Err), USB DR, internal
interrupt signals.
For more information, see
Freescale Semiconductor
0–31 INT n Each implemented bit (listed in
Bits Name
defines the bit fields of SIPNR_L.
System Internal Interrupt Group A Priority Register (SIPRR_A)
received, the interrupt controller sets the corresponding SIPNR bit. When a pending interrupt is handled, the user
clears the SIPNR bit by clearing the corresponding event register bit.
SIPNR bits are read only. Writing to this register has no effect.
Note that the SIPNR bit positions are not changed according to their relative priority.
For unimplemented bits, writes are ignored, read = 0.
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
Table 8-9. SIPNR_L/SIFCR_L/SIMSR_L Bit Assignments (continued)
Figure
Section 8.6.3, “Internal Interrupts Group Relative
8-6, defines the priority between TSEC1 transmit request (TSEC1 Tx), TSEC1
Table 8-10. SIPNR_L Field Descriptions
Table
17–19
22–25
28–30
Bits
10
11
12
13
14
15
16
20
21
26
27
31
8-9) corresponds to an internal interrupt source. When an interrupt is
Description
GTM2
GTM6
GTM3
GTM7
GTM1
GTM5
GPIO
Field
PMC
DDR
LBC
—
—
—
—
—
Integrated Programmable Interrupt Controller (IPIC)
Priority.”
8-13