MPC8313ZQADDC Freescale Semiconductor, MPC8313ZQADDC Datasheet - Page 576

• Manufacturer Part Number: MPC8313ZQADDC
• Description: Microprocessors - MPU 8313 REV2.2 PB NO ENC
• Manufacturer: Freescale Semiconductor

Specifications of MPC8313ZQADDC

• Processor Series: MPC8313
• Core: e300
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 133 MHz
• Program Memory Size: 16 KB
• Data Ram Size: 16 KB
• Interface Type: I2C
• Mounting Style: SMD/SMT
• Package / Case: PBGA
• Number Of Programmable I/os: 32
• Number Of Timers: 4

DMA/Messaging Unit
12.4.1.2
This block contains the inbound doorbell register (IDR) and the outbound doorbell register (ODR). The
inbound doorbell allows a remote processor to set a bit in the register from the PCI bus. This, in turn,
generates an interrupt request to the on-chip interrupt controller that drives an interrupt line to the local
processor. The local processor can write to the ODR, which causes the outbound interrupt signal
PCI_INTA to assert, thus interrupting the remote processor on the PCI bus.
The interrupt to the local processor is cleared by writing 1 to the appropriate IDR bit. The interrupt to PCI
(PCI_INTA) is cleared by writing 1 to the appropriate ODR bit.
12.4.2
The DMA controller transfers blocks of data independent of the local processor or PCI hosts. Data
movement occurs on the PCI bus and/or CSB. The DMA module has four high-speed DMA channels,
which share buffer space in the IOS to facilitate the gathering and sending of data. Both the local processor
and PCI masters can initiate a DMA transfer.
Features of the DMA controller include the following:
Figure 12-18
12.4.3
The DMA controller operates in the following two modes:
12-16
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Four channels
Concurrent execution across multiple channels with programmable bandwidth control
All channels are accessible by local processor and remote PCI masters
Unaligned transfer capability
Data chaining and direct mode
Interrupt on completed segment, chain, and error
Direct mode, in direct mode, the DMA controller does not read a chain of descriptors from memory
but instead uses the current parameters in the DMA registers to start a DMA transfer. The DMA
DMA Controller
DMA Operation
Doorbell Registers (IDR and ODR)
shows a diagram of the DMA controller in the integrated device.
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
CSB
Figure 12-18. DMA Controller Block Diagram
DMA0
I/O Sequencer (IOS)
PCI Bus
DMA1
Interface Logic
DMA2
DMA3
Freescale Semiconductor