MPC8313ZQADDC Freescale Semiconductor, MPC8313ZQADDC Datasheet - Page 363

• Manufacturer Part Number: MPC8313ZQADDC
• Description: Microprocessors - MPU 8313 REV2.2 PB NO ENC
• Manufacturer: Freescale Semiconductor

Specifications of MPC8313ZQADDC

• Processor Series: MPC8313
• Core: e300
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 133 MHz
• Program Memory Size: 16 KB
• Data Ram Size: 16 KB
• Interface Type: I2C
• Mounting Style: SMD/SMT
• Package / Case: PBGA
• Number Of Programmable I/os: 32
• Number Of Timers: 4

In this mode all machine check interrupts are gathered by the IPIC unit and sent to the PowerPC core. If
the device performs as a PCI host, the interrupts of the other PCI agents should be connected to the
implementation’s IRQx signals and treated like normal external interrupts (sent to the core).
8.3.2
In core disable mode, all internal interrupts (including those from the PCI block) are routed to and from
the IPIC, the interrupts are then sent through the PCI_INTA signal to the PCI host CPU. Note that the core
interrupt signal is masked. The user should use in this mode only the int output interrupt type (should not
use cint or smi output interrupt types) to read an updated SIVCR. (See
Interrupt Control Register (SICNR),”
(SECNR).”)
In this mode, machine check interrupts are driven either on PCI_INTA or on MCP_OUT as level-sensitive
interrupts. SERCR[MCPR] (see
which external signal is used.
8.4
The following sections provide an overview and detailed descriptions of the IPIC signals.
8.4.1
The device has 5 distinct external interrupt request input signals (IRQ[0:4]) and one interrupt request
output signal (PCI_INTA). The IPIC interface signals are defined in
8.4.2
Table 8-2
Freescale Semiconductor
IRQ[0:4]
PCI_INTA
MCP_OUT
IRQ[0:4]
Signal
Name
External Signal Description
provides detailed descriptions of the external IPIC signals.
I/O
Core Disable Mode
Overview
Detailed Signal Descriptions
I
IRQ[0:4]
PCI_INTA
MCP_OUT
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
Interrupt request 0–4. The sense (level or edge) of each of these signals is programmable. All of these inputs
can be driven completely asynchronously.
Meaning
Timing Assertion—All of these inputs can be asserted completely asynchronously.
Port
State
Table 8-2. IPIC External Signals—Detailed Signal Descriptions
Asserted—When an external interrupt request signal is asserted, the priority is checked by the IPIC
Negated—There is no incoming interrupt from that source.
Negation—Interrupts programmed as level-sensitive must remain asserted until serviced.
External interrupts
Interrupt request output
Interrupt request output
unit, and the interrupt is conditionally passed to the processor.
Section 8.5.15, “System Error Control Register
Table 8-1. IPIC Signal Properties
and
Section 8.5.12, “System External Interrupt Control Register
Function
Description
Integrated Programmable Interrupt Controller (IPIC)
Table
Section 8.5.7, “System Internal
8-1.
I/O
O
O
I
(SERCR)”) controls
Reset Requires Pull Up
—
Z
Z
Yes
Yes
Yes
8-5