MPC8313ZQADDC Freescale Semiconductor, MPC8313ZQADDC Datasheet - Page 632

• Manufacturer Part Number: MPC8313ZQADDC
• Description: Microprocessors - MPU 8313 REV2.2 PB NO ENC
• Manufacturer: Freescale Semiconductor

Specifications of MPC8313ZQADDC

• Processor Series: MPC8313
• Core: e300
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 133 MHz
• Program Memory Size: 16 KB
• Data Ram Size: 16 KB
• Interface Type: I2C
• Mounting Style: SMD/SMT
• Package / Case: PBGA
• Number Of Programmable I/os: 32
• Number Of Timers: 4

PCI Bus Interface
Figure 13-49
During the turnaround-cycle following the address phase, the PCI_C/BE[3:0] signals indicate which byte
lanes are involved in the data phase. The turnaround-cycle must be enforced by the target with the
PCI_TRDY signal if using fast PCI_DEVSEL assertion. The earliest the target can provide valid data is
one cycle after the turnaround cycle. The target must drive the AD[31:0] signals when PCI_DEVSEL is
asserted except during the turnaround cycle.
The data phase completes when data is transferred, which occurs when both PCI_IRDY and PCI_TRDY
are asserted on the same clock edge. When either is negated, a wait cycle is inserted and no data is
transferred. To indicate the last data phase PCI_IRDY must be asserted when PCI_FRAME is negated.
A write transaction starts when PCI_FRAME is asserted for the first time and the PCI_C/BE[3:0] signals
indicate a write command.
13-50
PCI_C/BE[3:0]
PCI_C/BE[3:0]
shows an example of a burst read transaction.
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
PCI_DEVSEL
PCI_DEVSEL
PCI_AD[31:0]
PCI_AD[31:0]
PCI_FRAME
PCI_FRAME
PCI_TRDY
PCI_TRDY
PCI_IRDY
PCI_IRDY
PCI_CLK
PCI_CLK
Figure 13-50
ADDR
ADDR
CMD
CMD
Figure 13-50. Single Beat Write Example
Figure 13-49. Burst Read Example
BYTE ENABLES 1
shows an example of a single-beat write transaction.
DATA1
BYTE ENABLES
DATA
BYTE ENABLES 2
DATA2
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