MPC8313ZQADDC Freescale Semiconductor, MPC8313ZQADDC Datasheet - Page 74

• Manufacturer Part Number: MPC8313ZQADDC
• Description: Microprocessors - MPU 8313 REV2.2 PB NO ENC
• Manufacturer: Freescale Semiconductor

Specifications of MPC8313ZQADDC

• Processor Series: MPC8313
• Core: e300
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 133 MHz
• Program Memory Size: 16 KB
• Data Ram Size: 16 KB
• Interface Type: I2C
• Mounting Style: SMD/SMT
• Package / Case: PBGA
• Number Of Programmable I/os: 32
• Number Of Timers: 4

About This Book
lxxiv
•
•
•
•
•
•
•
•
•
•
Chapter 6, “Arbiter and Bus Monitor,”
device. Also, it describes the configuration, control, and status registers of the arbiter.
Chapter 7, “e300 Processor Core Overview,”
processor core and briefly describes how the functional units interact.
Chapter 8, “Integrated Programmable Interrupt Controller (IPIC),”
protocol, various types of interrupt sources controlled by the IPIC unit, and the IPIC registers with
some programming guidelines. It also provides a definition of the external interrupt signals and
their functions. In addition, the interrupt configuration, control, and status registers are described
in this chapter.
Chapter 9, “DDR Memory Controller,”
the MPC8313E. This fully programmable controller supports most DDR memories available
today, including both buffered and unbuffered devices. Dynamic power management and
auto-precharge modes simplify memory system design.
Chapter 10, “Enhanced Local Bus Controller,”
of the MPC8313E. It describes the external signals and the memory-mapped registers as well as a
functional description of the general-purpose chip-select machine (GPCM), Flash control machine
(FCM), and user-programmable machines (UPMs) of the eLBC. Also, it includes an initialization
and applications information section with many specific examples of its use.
Chapter 11, “Sequencer
ports, using a buffer pool to minimize blocking. It also provides address translation on outbound
PCI transactions.
Chapter 12, “DMA/Messaging Unit
DMA controller of the MPC8313E. The channels share buffer space in the IOS to facilitate the
gathering and sending of data. The DMA/messaging unit supports communication between two
processors on different buses, for example, a local processor and a processor on a PCI bus. This
communication unit operates with generic messages and doorbell registers. This block also
provides a DMA controller that transfers blocks of data independent of the local processor or PCI
hosts.
Chapter 13, “PCI Bus Interface,”
Bus Specification, Rev. 2.3. This chapter provides a basic description of PCI bus operations. The
specific emphasis is directed at how this device implements the PCI specification.
Chapter 14, “Security Engine (SEC) 2.2,”
computationally intensive security functions, such as key generation and exchange, authentication,
and bulk encryption from the e300 core of the MPC8313E. It is optimized to process all the
algorithms associated with IPSec. The SEC 2.2 (implemented in the MPC8313E) is derived from
integrated security cores found in other members of the PowerQUICC family, including SEC 1.0,
the version implemented in the MPC8272/MPC8248. Note that the MPC8313 does not support a
security engine.
Chapter 15, “Enhanced Three-Speed Ethernet Controllers,”
three-speed Ethernet controllers on the MPC8313E. These controllers provide 10/100/1Gb
Ethernet support with a set of media-independent interface options including MII, RMII, GMII,
SGMII and RTBI. They are backward compatible with PowerQUICC III TSEC controllers.
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
,”
describes how the I/O sequencer (IOS) switches transactions among its
describes the PCI interface, which complies with the PCI Local
,”
describes the four-channel high speed general-purpose
provides an overview of the arbiter in the MPC8313E
describes the 32-bit DDR SDRAM memory controller of
describes the SEC 2.2, which is designed to offload
provides an overview of the basic functionality of the
describes the enhanced local bus controller (eLBC)
describes the two enhanced
describes the IPIC interrupt
Freescale Semiconductor