MPC8313ZQADDC Freescale Semiconductor, MPC8313ZQADDC Datasheet - Page 972

• Manufacturer Part Number: MPC8313ZQADDC
• Description: Microprocessors - MPU 8313 REV2.2 PB NO ENC
• Manufacturer: Freescale Semiconductor

Specifications of MPC8313ZQADDC

• Processor Series: MPC8313
• Core: e300
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 133 MHz
• Program Memory Size: 16 KB
• Data Ram Size: 16 KB
• Interface Type: I2C
• Mounting Style: SMD/SMT
• Package / Case: PBGA
• Number Of Programmable I/os: 32
• Number Of Timers: 4

Universal Serial Bus Interface
16-44
Offset 0x2_3500
Reset
Reset
16–18
19–20
0–13
Bits
14
15
21
22
23
W
W
R
R
16
0
CLKIN_SEL[1:0] Select the clock source for the UTMI PHY PLL reference clock. The reference clock can be
PHY_CLK_SEL
UTMI_PHY_EN
PLL_RESET
—
PHY_CLK_
WU_INT
VALID
Name
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
18
—
—
CLKIN_
19
SEL
20
Figure 16-34. USB General-Purpose Register (CONTROL)
Reserved, must be cleared.
Indicates whether the PHY clock is valid (read only). When in UTMI mode, this bit reflects the value
of the UTMI PHY ClkValid signal. In ULPI mode, this bit reflects the inverted ULPI DIR. In ULPI
mode, this bit is not valid if the USB I/O have not been configured and after the USB_EN signal is
asserted.
0 USB PHY clock is not valid
1 USB PHY clock is valid
Reflects the state of the wake up interrupt. The wake up interrupt signal is asserted when a
wake-up event occurs while in a low-power suspend state. If WU_INT_EN is set, this WU_INT
signal generates an interrupt to the system to indicate wake up servicing is required. WU_INT will
remain set until the USB controller is exited from the low power by clearing the PORTSC[PHCD]
bit.
0 Normal operation or Low Power mode waiting for wakeup event
1 Low power wakeup event has occurred
Reserved, must be cleared.
sourced from the USB_CLK or divide by 1 or 2 of the SYS_CLK. These bits are not relevant when
in ULPI mode.
00 Reference clock is USB_CLK
01 Reference clock is USB_CLK
10 Reference clock is SYS_CLK
11 Reference clock is SYS_CLK divided by 2
Select the source of the USB link controller transceiver clock. When cleared the UTMI PHY is the
source of the clock. When set, the clock is sourced from the external ULPI PHY.
0 UTMI is clock source
1 ULPI is clock source
Enable the UTMI PHY. The UTMI PHY is reset when placed in the disable mode.
0 UTMI PHY disabled
1 UTMI PHY enabled
Reset the UTMI PHY PLL. This bit is not self clearing and must be cleared to complete the reset
sequence.
0 UTMI PHY in normal operating state
1 Put UTMI PHY in reset state
PHY_CLK
_SEL
21
Table 16-37. CONTROL Field Descriptions
PHY_EN
UTMI_
22
RESET
PLL_
—
23
REFSEL
All zeros
All zeros
24
25
Description
PORT
OTG_
26
OTG_ON
KEEP_
27
LSF_
EN
28
USB_
EN
13
29
Freescale Semiconductor
PHY_CLK
INT_EN
_VALID
WU_
14
30
Access: Mixed
WU_INT
INT_EN
ULPI_
15
31