MPC8313ZQADDC Freescale Semiconductor, MPC8313ZQADDC Datasheet - Page 766

• Manufacturer Part Number: MPC8313ZQADDC
• Description: Microprocessors - MPU 8313 REV2.2 PB NO ENC
• Manufacturer: Freescale Semiconductor

Specifications of MPC8313ZQADDC

• Processor Series: MPC8313
• Core: e300
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 133 MHz
• Program Memory Size: 16 KB
• Data Ram Size: 16 KB
• Interface Type: I2C
• Mounting Style: SMD/SMT
• Package / Case: PBGA
• Number Of Programmable I/os: 32
• Number Of Timers: 4

Offset eTSEC1:0x2_4300; eTSEC2:0x2_5300
Reset
Reset
Enhanced Three-Speed Ethernet Controllers
15.5.3.3
This section describes the control and status registers that are used specifically for receiving Ethernet
frames. All of the registers are 32 bits wide.
15.5.3.3.1
The RCTRL register is programmed by the user and controls the operational mode of the receiver. It must
be written only after a system reset (at initialization) or after a graceful receive stop has completed.
Figure 15-22
Table 15-27
15-48
W
W
11–15
R
R
8–10
Bits
0–6
16
7
—
16
0
Name
LFC VLEX FILREN FSQEN GHTX IPCSEN TUCSEN
PAL
17
TS
—
—
—
describes the fields of the RCTRL register.
eTSEC Receive Control and Status Registers
describes the RCTRL register.
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
Receive Control Register (RCTRL)
18
Reserved
Timestamp incoming packets as padding bytes. PAL field is set to 8 if the PAL field is programmed to less
than 8. Must be set to zero if TMR_CTRL[TE]=0.
Reserved
Packet alignment padding length. If not zero, PAL (1–31) bytes of zero padding are inserted before the
start of each received frame, but following the RxFCB if TOE is enabled. For Ethernet where optional
preamble extraction is enabled, the padding appears before the preamble, otherwise the padding
precedes the layer 2 header. The value of PAL can be set so that the start of the IP header in the receive
data buffer is aligned to a 32-bit boundary. Normally, setting PAL = 2 provides minimal padding to ensure
such alignment of the IP header.
Note that the minimum zero padding value for this field should be PAL–8 if the TS field is set and 0 when
PAL is < 8.
Reserved
19
—
20
Figure 15-22. RCTRL Register Definition
Table 15-27. RCTRL Field Descriptions
21
22
All zeros
All zeros
TS
23
7
Description
24
PRSDEP
8
25
—
10
—
26
BC_REJ PROM RSF EMEN —
11
27
Freescale Semiconductor
28
Access: Read/Write
PAL
29
30
15
31