MPC8313ZQADDC Freescale Semiconductor, MPC8313ZQADDC Datasheet - Page 481

• Manufacturer Part Number: MPC8313ZQADDC
• Description: Microprocessors - MPU 8313 REV2.2 PB NO ENC
• Manufacturer: Freescale Semiconductor

Specifications of MPC8313ZQADDC

• Processor Series: MPC8313
• Core: e300
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 133 MHz
• Program Memory Size: 16 KB
• Data Ram Size: 16 KB
• Interface Type: I2C
• Mounting Style: SMD/SMT
• Package / Case: PBGA
• Number Of Programmable I/os: 32
• Number Of Timers: 4

Offset 0x0_50D4
10.3.1.16 Clock Ratio Register (LCRR)
The clock ratio register, shown in
provides configuration bits for extra delay cycles for address and control signals.
Reset
Table 10-23
Freescale Semiconductor
14–15
16–26
27–31
0–13
Bits
W
R
1
0
CLKDIV
Name
EADC
—
—
0
describes LCRR fields.
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
For proper operation of the system, it is required that this register setting
will not be altered while local bus memories or devices are being accessed.
Special care needs to be taken when running instructions from an eLBC
memory.
0 0
Reserved
External address delay cycles of LCLK. Defines the number of cycles for the assertion of LALE.
00 4
01 1
10 2
11 3
Reserved
System clock divider. Sets the frequency ratio between the system clock and the local bus clock. The
system clock is equivalent to csb_clk or twice csb_clk (if RCWL[LBIUCM] is set). Only the values shown
below are allowed.
Note: It is critical that no transactions are being executed via the local bus while CLKDIV is being
00000–00001 Reserved
00010 2
00011 Reserved
00100 4
00101–00111 Reserved
01000 8
01001–11111 Reserved
0
modified. As such, prior to modification, the user must ensure that code is not executing out of the
local bus. Once LCRR[CLKDIV] is written, the register should be read, and then an isync should
be executed.
0
—
0
0
Figure 10-20. Clock Ratio Register (LCRR)
0
Figure
Table 10-23. LCRR Field Descriptions
0 0 0
10-20, sets the system clock to eLBC bus frequency ratio. It also
0
13 14 15 16
0
NOTE
EADC
0
0
Description
0
0
0
0
0
—
0
0
0
Enhanced Local Bus Controller
0
0
26 27
0
Access: Read/Write
0
n
CLKDIV
n 0
10-33
30 31
0