MPC8313ZQADDC Freescale Semiconductor, MPC8313ZQADDC Datasheet - Page 308

• Manufacturer Part Number: MPC8313ZQADDC
• Description: Microprocessors - MPU 8313 REV2.2 PB NO ENC
• Manufacturer: Freescale Semiconductor

Specifications of MPC8313ZQADDC

• Processor Series: MPC8313
• Core: e300
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 133 MHz
• Program Memory Size: 16 KB
• Data Ram Size: 16 KB
• Interface Type: I2C
• Mounting Style: SMD/SMT
• Package / Case: PBGA
• Number Of Programmable I/os: 32
• Number Of Timers: 4

Arbiter and Bus Monitor
6.2.4
Arbiter interrupt definition register (AIDR) determines the interrupt that responds to different error
conditions. Setting a bit defines the corresponding interrupt as MCP interrupt; clearing a bit defines the
corresponding interrupt as regular interrupt.
Table 6-5
6-6
Offset 0x10
Reset
0–25
Bits
26
27
28
29
30
31
W
R
0
Name
ETEA
ECW
describes AIDR fields.
RES
DTO
ATO
AO
—
Arbiter Interrupt Definition Register (AIDR)
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
Write reserved, read = 0
Transfer error.Detection of transfer error by one of the slaves interrupt definition.
0 Detection of transfer error by one of the slaves causes regular interrupt.
1 Detection of transfer error by one of the slaves causes MCP interrupt.
Reserved transfer type. Transaction with reserved transfer type interrupt definition.
0 Transaction with reserved transfer type causes regular interrupt.
1 Transaction with reserved transfer type causes MCP interrupt.
External control word transfer type. Transaction with external control word transfer type interrupt definition.
0 Transaction with external control word transfer type causes regular interrupt.
1 Transaction with external control word transfer type causes MCP interrupt.
Address only transfer type. Transaction with address only transfer type interrupt definition.
0 Transaction with address only transfer type causes regular interrupt.
1 Transaction with address only transfer type causes MCP interrupt.
Data time out. Data tenure time out interrupt definition.
0 Data tenure time out causes regular interrupt.
1 Data tenure time out causes MCP interrupt.
0 Address tenure time out causes regular interrupt.
1 Address tenure time out causes MCP interrupt.
Address time out. Address tenure time out interrupt definition.
Figure 6-4. Arbiter Interrupt Definition Register (AIDR)
Table 6-5. AIDR Field Descriptions
—
Figure 6-4
All zeros
shows the fields of AIDR.
Description
25
ETEA RES ECW AO DTO ATO
26
27
Freescale Semiconductor
Access: User read/write
28
29
30
31