MPC8313ZQADDC Freescale Semiconductor, MPC8313ZQADDC Datasheet - Page 414

• Manufacturer Part Number: MPC8313ZQADDC
• Description: Microprocessors - MPU 8313 REV2.2 PB NO ENC
• Manufacturer: Freescale Semiconductor

Specifications of MPC8313ZQADDC

• Processor Series: MPC8313
• Core: e300
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 133 MHz
• Program Memory Size: 16 KB
• Data Ram Size: 16 KB
• Interface Type: I2C
• Mounting Style: SMD/SMT
• Package / Case: PBGA
• Number Of Programmable I/os: 32
• Number Of Timers: 4

DDR Memory Controller
9-20
17–23
24–25
Bits
15
16
26
27
28
29
30
31
BA_INTLV_CTL
MEM_HALT
x32_EN
PCHB8
2T_EN
Name
HSE
—
—
—
BI
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
Table 9-12. DDR_SDRAM_CFG Field Descriptions (continued)
Reserved
Enable 2T timing.
0 1T timing is enabled. The DRAM command/address are held for only 1 cycle on the DRAM bus.
1 2T timing is enabled. The DRAM command/address are held for 2 full cycles on the DRAM bus
Note: RD_EN and 2T_EN must not both be set at the same time.
(All unlisted field values are reserved.)
0000000 No external memory banks are interleaved
1000000 External memory banks 0 and 1 are interleaved
Reserved
0 Either x8 or x16 discrete DRAM chips are used. In this mode, each data byte has a dedicated
1 x32 discrete DRAM chips are used. In this mode, DQS0 is used to capture DQ[0:31].
0 MA[10] is used to indicate the auto-precharge and precharge all commands.
1 MA[8] is used to indicate the auto-precharge and precharge all commands.
If x32_EN is cleared, then PCHB8 should be cleared as well.
Sets I/O driver impedance to half strength. This impedance is used by the MDIC, address/command,
data, and clock impedance values, but only if automatic hardware calibration is disabled and the
corresponding group's software override is disabled in the DDR control driver register(s) described
in
automatic hardware calibration.
0 I/O driver impedance is configured to full strength.
1 I/O driver impedance is configured to half strength.
Reserved
data read/write transactions to DDR SDRAM until the bit is cleared again. This can be used when
bypassing initialization and forcing MODE REGISTER SET commands through software.
0 DDR controller accepts new transactions.
1 DDR controller finishes any remaining transactions, and then it remains halted until this bit is
Bypass initialization
0 DDR controller cycles through initialization routine based on SDRAM_TYPE
1 Initialization routine is bypassed. Software is responsible for initializing memory through
Bank (chip select) interleaving control. Set this field only if you wish to use bank interleaving.
x32 enable.
Precharge bit 8 enable.
Global half-strength override
DDR memory controller halt. When this bit is set, the memory controller does not accept any new
Section 5.3.2.8, “DDR Control Driver Register
for every DRAM transaction. However, the chip select is only held for the second cycle.
corresponding data strobe.
cleared by software.
DDR_SDRAM_MODE2 register. If software is initializing memory, then the MEM_HALT bit can be
set to prevent the DDR controller from issuing transactions during the initialization sequence.
Note that the DDR controller does not issue a DLL reset to the DRAMs when bypassing the
initialization routine, regardless of the value of DDR_SDRAM_CFG[DLL_RST_DIS]. If a DLL
reset is required, then the controller should be forced to enter and exit self refresh after the
controller is enabled.
Description
(DDRCDR).” This bit should be cleared if using
S
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