MPC8313ZQADDC Freescale Semiconductor, MPC8313ZQADDC Datasheet - Page 253

• Manufacturer Part Number: MPC8313ZQADDC
• Description: Microprocessors - MPU 8313 REV2.2 PB NO ENC
• Manufacturer: Freescale Semiconductor

Specifications of MPC8313ZQADDC

• Processor Series: MPC8313
• Core: e300
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 133 MHz
• Program Memory Size: 16 KB
• Data Ram Size: 16 KB
• Interface Type: I2C
• Mounting Style: SMD/SMT
• Package / Case: PBGA
• Number Of Programmable I/os: 32
• Number Of Timers: 4

Table 5-47
5.6.5
The PIT programmable register map occupies 32 bytes of memory-mapped space. Reading undefined
portions of the memory map returns all zeros; writing has no effect.
All PIT registers are 32 bits wide and reside on 32-bit address boundaries and should only be accessed as
32-bit quantities.
All addresses used in this chapter are offsets from PIT base, as defined in
Table 5-48
5.6.5.1
The periodic interval timer control register (PTCNR), shown in
PIT functions. The register can be read at any time.
Freescale Semiconductor
Offset 0x00
Reset
0x14–0x1F
PIT_CLK
Signal
Offset
0x0C
0x00
0x04
0x08
0x10
W
R
0
describes of the external PIT signal.
shows the PIT memory map.
PIT Memory Map/Register Definition
Periodic Interval Timer Control Register (PTCNR)
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
Periodic interval timer control register (PTCNR)
Periodic interval timer load register (PTLDR)
Periodic interval timer prescale register (PTPSR)
Periodic interval timer counter register (PTCTR)
Periodic interval timer event register (PTEVR)
Reserved
I/O
I
This signal is used as the timebase for the periodic interval timer module.
Meaning
Timing
Figure 5-33. Periodic Interval Timer Control Register (PTCNR)
Table 5-47. PIT External Signal—Detailed Signal Descriptions
State
Table 5-48. PIT Register Address Map
Register
—
All zeros
Description
Figure
—
—
Access
R/W
R/W
R/W
w1c
—
R
5-33, is used to enable the different
23
Chapter 2, “Memory Map.”
CLEN CLIN
24
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
Reset Value
—
25
26
System Configuration
Access: Read/Write
—
5.6.5.1/5-45
5.6.5.2/5-46
5.6.5.3/5-47
5.6.5.4/5-47
5.6.5.5/5-47
Section/
Page
30
PIM
5-45
31