MPC8313ZQADDC Freescale Semiconductor, MPC8313ZQADDC Datasheet - Page 570

• Manufacturer Part Number: MPC8313ZQADDC
• Description: Microprocessors - MPU 8313 REV2.2 PB NO ENC
• Manufacturer: Freescale Semiconductor

Specifications of MPC8313ZQADDC

• Processor Series: MPC8313
• Core: e300
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 133 MHz
• Program Memory Size: 16 KB
• Data Ram Size: 16 KB
• Interface Type: I2C
• Mounting Style: SMD/SMT
• Package / Case: PBGA
• Number Of Programmable I/os: 32
• Number Of Timers: 4

DMA/Messaging Unit
12-10
17–16
15–14
11–10
Bits
9–8
6–4
20
19
18
13
12
7
DMSEN Direct mode snoop enable. This bit controls snooping of direct mode DMA transactions.
DAHTS
SAHTS
EOTIE
Name
DAHE
SAHE
IRQS
PRC
—
—
—
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
0 Snooping is disabled
1 Snooping is enabled
Interrupt steer. This bit determines the destination of the DMA interrupts.
0 All DMA interrupts are routed to the on-chip interrupt controller
1 All DMA interrupts are routed to the PCI bus through PCI_INTA
Reserved
Destination address hold transfer size. This field indicates the transfer size used for each transaction when
DAHE is 1. The byte count register must be in multiples of the size, and the destination address register
must be aligned based on the size.
00 1 byte
01 2 bytes
10 4 bytes
11 8 bytes
Source address hold transfer size. This field indicates the transfer size used for each transaction when
SAHE is 1. The byte count register must be in multiples of the size, and the source address register must
be aligned based on the size.
00 1 byte
01 2 bytes
10 4 bytes
11 8 bytes
Destination address hold enable. This bit allows the DMA controller to hold the destination address constant
for every transfer. The size used for transfer is indicated by DAHTS. Note that hardware supports only
aligned transfers for this feature.
0 Do not hold the destination address constant
1 Hold the destination address constant
Note: The DMA does not support address hold for both the source and the destination at the same transfer.
Source address hold enable. This bit allows the DMA controller to hold the source address constant for
every transfer. The size used for transfer is indicated by SAHTS. Note that hardware supports only aligned
transfers for this feature.
0 Do not hold the source address constant
1 Hold the source address constant
Note: The DMA does not support address hold for both the source and the destination at the same transfer.
PCI read command. This field indicates the type of PCI read command to use.
00 Reserved
01 PCI read line
10 PCI read multiple
11 Reserved
Reserved
End-of-transfer interrupt enable. This bit determines whether an interrupt is generated at the completion of
a DMA transfer. End-of-transfer is defined as the end of a direct mode transfer or in chaining mode, as the
end of the transfer of the last segment of a chain.
0 No EOT interrupt is generated
1 EOT interrupt is generated
Reserved
Table 12-10. DMAMR n Field Descriptions (continued)
Description
Freescale Semiconductor