MPC8313ZQADDC Freescale Semiconductor, MPC8313ZQADDC Datasheet - Page 1021

• Manufacturer Part Number: MPC8313ZQADDC
• Description: Microprocessors - MPU 8313 REV2.2 PB NO ENC
• Manufacturer: Freescale Semiconductor

Specifications of MPC8313ZQADDC

• Processor Series: MPC8313
• Core: e300
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 133 MHz
• Program Memory Size: 16 KB
• Data Ram Size: 16 KB
• Interface Type: I2C
• Mounting Style: SMD/SMT
• Package / Case: PBGA
• Number Of Programmable I/os: 32
• Number Of Timers: 4

The scheduling cases are:
Freescale Semiconductor
•
•
Periodic Schedule
Case 1: The normal scheduling case is where the entire split transaction is completely bounded by
a frame (H-Frame in this case).
Case 2a through Case 2c: The USB 2.0 hub pipeline rules states clearly, when and how many
complete-splits must be scheduled to account for earliest to latest execution on the full/low-speed
link. The complete-splits may span the H-Frame boundary when the start-split is in micro-frame 4
or later. When this occurs, the H-Frame to B-Frame alignment requires that the queue head be
reachable from consecutive periodic frame list locations. System software cannot build an efficient
schedule that satisfies this requirement unless it uses FSTNs.
layout of the periodic schedule.
HS/FS/LS Bus
End of Frame
End of Frame
End of Frame
Normal Case
Micro-Frame
Micro-Frame
Case 2a:
Case 2b:
Case 2c:
Case 1:
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
B-Frame N–1
Figure 16-53. Split Transaction, Interrupt Scheduling Boundary Conditions
7
6
0
7
S
1
0
2
1
C0
3
2
H-Frame N
C1
4
3
B-Frame N
C2
S
5
4
S
6
5
C0
Figure 16-54
S
7
6
C0
C1
0
7
Universal Serial Bus Interface
C0
C1
C2
illustrates the general
1
0
C1
C2
B-Frame N+1
16-93