MPC8313ZQADDC Freescale Semiconductor, MPC8313ZQADDC Datasheet - Page 311

• Manufacturer Part Number: MPC8313ZQADDC
• Description: Microprocessors - MPU 8313 REV2.2 PB NO ENC
• Manufacturer: Freescale Semiconductor

Specifications of MPC8313ZQADDC

• Processor Series: MPC8313
• Core: e300
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 133 MHz
• Program Memory Size: 16 KB
• Data Ram Size: 16 KB
• Interface Type: I2C
• Mounting Style: SMD/SMT
• Package / Case: PBGA
• Number Of Programmable I/os: 32
• Number Of Timers: 4

6.2.7
Arbiter event address register (AEADR) reports the address of transaction that causes the error, which is
specified in the event register. See
AEADR is cleared only by power-on reset. The address of the first error event is stored. Note that this
means that AEADR does not change its value when AER is not clear. As AEADR is not effected by soft
or hard reset, software can read this register and determine the cause of the bus failure, even if the bus
failure had caused a deadlock situation. Refer to
information.
Figure 6-7
Table 6-8
Freescale Semiconductor
27–31
0–31
Bits
Bits
Offset 0x1C
Reset
W
R
0
TTYPE
describes AEADR fields.
ADDR
Name
Name
shows the fields of AEADR.
Arbiter Event Address Register (AEADR)
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
Transfer type.
00000
00001
00010
00011
00100
00101
00110
00111
0100x
0101x
0110x
01110
Address of the event reported in AEATR register. See
(AEATR),”
Address-only
Address-only
Single-beat or burst write
Reserved
Address-only
Reserved
Burst write
Reserved
Address-only
Single-beat or burst read
Address-only
Burst read
Figure 6-7. Arbiter Event Address Register (AEADR)
for more information.
Table 6-7. AEATR Field Descriptions (continued)
Table 6-8. AEADR Field Descriptions
Section 6.2.3, “Arbiter Event Register (AER),”
Section 6.4.2, “Error Handling Sequence,”
All zeros
ADDR
Description
Description
01111
10000
1XX01
10010
1XX11
10100
10110
11000
11010
11100
11110
Section 6.2.6, “Arbiter Event Attributes Register
Reserved
Address-only
Reserved
Single-beat write
Reserved
ecowx—Illegal single-beat write
Reserved
Address-only
Single-beat or burst read
eciwx—Illegal single-beat read
Burst read
for more information.
Access: User read/write
Arbiter and Bus Monitor
for more
6-9
31