MPC8313ZQADDC Freescale Semiconductor, MPC8313ZQADDC Datasheet - Page 412

• Manufacturer Part Number: MPC8313ZQADDC
• Description: Microprocessors - MPU 8313 REV2.2 PB NO ENC
• Manufacturer: Freescale Semiconductor

Specifications of MPC8313ZQADDC

• Processor Series: MPC8313
• Core: e300
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 133 MHz
• Program Memory Size: 16 KB
• Data Ram Size: 16 KB
• Interface Type: I2C
• Mounting Style: SMD/SMT
• Package / Case: PBGA
• Number Of Programmable I/os: 32
• Number Of Timers: 4

1
19–21 WR_DATA_DELAY Write command to write data strobe timing adjustment. Controls the amount of delay applied to the
23–25
26–31
DDR Memory Controller
9.4.1.7
The DDR SDRAM control configuration register, shown in
specifies certain operating features such as self refreshing, error checking and correcting, registered
DIMMs, and dynamic power management.
9-18
Offset 0x110
Reset
Reset
Bits
22
For CPO decodings other than 00000 and 11111, ‘READ_LAT’ is rounded up to the next integer value.
W
W
R
R
MEM_EN SREN
2T_EN
FOUR_ACT
16
0
0
CKE_PLS
Name
DDR SDRAM Control Configuration (DDR_SDRAM_CFG)
—
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
Figure 9-8. DDR SDRAM Control Configuration Register (DDR_SDRAM_CFG)
17
0
1
Table 9-11. TIMING_CFG_2 Field Descriptions (continued)
data and data strobes for writes. See
details.
000 0 clock delay
001 1/4 clock delay
010 1/2 clock delay
011 3/4 clock delay
Reserved
Minimum CKE pulse width (t
000 Reserved
001 1 cycle
010 2 cycles
Window for four activates (t
to 000001 for DDR1.
000000 Reserved
000001 1 cycle
000010 2 cycles
000011 3 cycles
000100 4 cycles
—
0
2
BA_INTLV_CTL
RD_EN — SDRAM_TYPE
0
3
0
4
0
5
1
FAW
CKE
). This is applied to DDR2 with eight logical banks only. Must be set
)Can be set to 001 for DDR1.
23
0
7
All zeros
24 25
0 0
8
Section 9.5.7, “DDR SDRAM Write Timing Adjustments,”
—
—
9
100 1 clock delay
101 5/4 clock delay
110 3/2 clock delay
111 Reserved
011 3 cycles
100 4 cycles
101–111 Reserved
...
01001119 cycles
010100 20 cycles
010101–111111 Reserved
Description
DYN_PWR
Figure
x32_EN
10
26
0
9-8, enables the interface logic and
PCHB8 HSE
11
27
0
DBW
12
28
0
8_BE
Freescale Semiconductor
—
13
29
0
Access: Read/Write
MEM_HALT
NCAP
14
30
0
—
BI
15
31
0
for