MPC8313ZQADDC Freescale Semiconductor, MPC8313ZQADDC Datasheet - Page 921

• Manufacturer Part Number: MPC8313ZQADDC
• Description: Microprocessors - MPU 8313 REV2.2 PB NO ENC
• Manufacturer: Freescale Semiconductor

Specifications of MPC8313ZQADDC

• Processor Series: MPC8313
• Core: e300
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 133 MHz
• Program Memory Size: 16 KB
• Data Ram Size: 16 KB
• Interface Type: I2C
• Mounting Style: SMD/SMT
• Package / Case: PBGA
• Number Of Programmable I/os: 32
• Number Of Timers: 4

Freescale Semiconductor
other information about the link is also returned (Extend Status, No pre, Remote Fault, An Ability, Link status, extend Ability)
read the MII Mgmt AN Link Partner Base Page Ability register and check bits 9 and 10 (Half and Full Duplex)
MII Mgmt AN Link Partner Base Page Ability ---> [0000_0000_0000_0000_0000_00X_1110_0000]
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
read the MII Mgmt AN Expansion register and check bits 13 and 14 (NP Able and Page Rx’d)
Perform an MII Mgmt read cycle of AN Link Partner Base Page Ability Register (Optional)
(Uses the PHY address (2) and Register address (2) placed in MIIMADD register),
(Uses the PHY address (2) and Register address (6) placed in MIIMADD register),
(Uses the PHY address (2) and Register address (5) placed in MIIMADD register),
MII Mgmt AN Expansion ---> [0000_0000_0000_0000_0000_0000_0000_0110]
Table 15-173. RMII Mode Register Initialization Steps (continued)
RBASE0–RBASE7[LLLL_LLLL_LLLL_LLLL_LLLL_LLLL_LLLL_L000]
TBASE0–TBASE7[LLLL_LLLL_LLLL_LLLL_LLLL_LLLL_LLLL_L000]
Initialize (Empty) Receive Descriptor ring and fill with empty buffers
Initialize (Empty) Transmit Descriptor ring and fill buffers with Data
MIIMSTAT ---> [0000_0000_0000_0000_0000_0000_0010_0000]
MACCFG1[0000_0000_0000_0000_0000_0000_0000_0101]
DMACTRL[0000_0000_0000_0000_0000_0000_0000_0000]
MIIMADD[0000_0000_0000_0000_0000_0010_0000_0110]
MIIMADD[0000_0000_0000_0000_0000_0010_0000_0101]
GADDR n [0000_0000_0000_0000_0000_0000_0000_0000]
Perform an MII Mgmt read cycle of AN Expansion Register
IEVENT[0000_0000_0000_0000_0000_0000_0000_0000]
RCTRL[0000_0000_0000_0000_0000_0000_0000_0000]
IMASK[0000_0000_0000_0000_0000_0000_0000_0000]
read the MIIMSTAT register and check bit 10 (AN Done)
Perform an MII Mgmt read cycle of Status Register
Initialize DMACTRL (Optional)
Initialize GADDR n (Optional)
Initialize RBASE0–RBASE7,
Initialize TBASE0–TBASE7,
Set MIIMCOM[Read Cycle]
Set MIIMCOM[Read Cycle]
Set MIIMCOM[Read Cycle]
Initialize RCTRL (Optional)
Initialize IMASK (Optional)
Enable Transmit Queues
Enable Receive Queues
Clear IEVENT register,
Enable Rx and Tx,
Initialize RQUEUE
Initialize TQUEUE
Enhanced Three-Speed Ethernet Controllers
15-203