MPC8313ZQADDC Freescale Semiconductor, MPC8313ZQADDC Datasheet - Page 893

• Manufacturer Part Number: MPC8313ZQADDC
• Description: Microprocessors - MPU 8313 REV2.2 PB NO ENC
• Manufacturer: Freescale Semiconductor

Specifications of MPC8313ZQADDC

• Processor Series: MPC8313
• Core: e300
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 133 MHz
• Program Memory Size: 16 KB
• Data Ram Size: 16 KB
• Interface Type: I2C
• Mounting Style: SMD/SMT
• Package / Case: PBGA
• Number Of Programmable I/os: 32
• Number Of Timers: 4

The algorithm checks registers TQUEUE[EN0–EN7] for
ring_empty(),
throughput for that ring is:
15.6.5
The eTSEC DMA subsystem is designed to be able to support simultaneous receive and transmit traffic at
gigabit line rates. If the host memory has sufficient bandwidth to support such line rates, then the principle
cause of overflow on receive traffic is due to a lack of Rx BDs. Thus, the long term receive throughput is
determined by the rate at which software can process receive traffic. If a user desires to prevent dropped
packets, they can inform the far-end link to stop transmission while the software processing catches up
with the backlog.
To avoid overflow in the latter case, back pressure must be applied to the far-end transmitter before the Rx
descriptor controller encounters a non-empty BD and halts with a BSY error. As there is lag between
application of back-pressure and response of the far-end, the pause request must be issued while there are
still BDs free in the ring. In the traditional eTSEC descriptor ring programming model, there is no way for
hardware to know how many free BDs are available, so software must initiate any pause requests required
during operation. If software is backlogged, the request may be not be issued in time to prevent BSY errors.
To allow the eTSEC to generate the pause request automatically, additional information (a pointer the last
free BD and ring length) is required.
15.6.5.1
Ultimately, the rate of data reception is determined by how quickly software can release buffers back into
the receive ring(s). Each time a buffer is freed, the associated BD has its empty bit set and hardware is free
to consume both. Thus the number of free BDs in a given Rx ring indicates how close hardware is to the
end of that ring. To prevent data loss, back pressure should be applied when the number of free BDs drops
below some critical level. The number of BDs that can be consumed by an incoming packet stream while
back-pressure takes effect is determined by several factors, such as: receive traffic profile, transmit traffic
profile, Rx buffer size, physical transmission time between eTSEC and far-end device and intra-device
latency. Theoretically, the worst case is as follows:
Freescale Semiconductor
endloop
rate of queue[k] (K = 1 to 7) = (available bandwidth) * WTk/(sum(WTi) + 6WT0)
rate of queue(0) = (available bandwidth) * 7 * WT0/(sum(WTi) + 6WT0)
where i = 0 to 7
if not ring_empty(ring) then
endif
while credit[ring] > 0 loop
endloop
credit[ring] = credit[ring] + weight[ring];
transmit_frame(ring);
credit[ring] = credit[ring] - frame_size;
if ring_empty(ring) then
endif
Lossless Flow Control
Back Pressure Determination through Free Buffers
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
and TRxWT for
credit[ring] = 0;
weight()
. For TxBD ring k, having a weight WTk, the long term average
enabled()
, TSTAT[THLT0–THLT7] for
Enhanced Three-Speed Ethernet Controllers
15-175