MPC8313ZQADDC Freescale Semiconductor, MPC8313ZQADDC Datasheet - Page 1094

• Manufacturer Part Number: MPC8313ZQADDC
• Description: Microprocessors - MPU 8313 REV2.2 PB NO ENC
• Manufacturer: Freescale Semiconductor

Specifications of MPC8313ZQADDC

• Processor Series: MPC8313
• Core: e300
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 133 MHz
• Program Memory Size: 16 KB
• Data Ram Size: 16 KB
• Interface Type: I2C
• Mounting Style: SMD/SMT
• Package / Case: PBGA
• Number Of Programmable I/os: 32
• Number Of Timers: 4

I
Table 17-9
17.4
The I
or slave transmitter. If boot sequencer mode is selected, the I
the boot sequence has completed.
17.4.1
A standard I
Figure 17-8
address components of the I
subsections.
17-10
2
C Interfaces
Bits
0–1
2–7
•
•
•
•
SDA
SDA
SCL
SCL
2
C unit always performs as a slave receiver as a default, unless explicitly programmed to be a master
START condition
Slave target address transmission
Data transfer
STOP condition
START
START
Name
DFSR Digital filter sampling rate. To assist in filtering out signal noise, the sample rate is programmed. DFSR is used
Functional Description
—
shows the I2CnDFSRR field descriptions.
Transaction Protocol
2
shows the interaction of these four parts with the calling address, data byte, and new calling
C transfer consists of the following:
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
A0 A1 A2 A3 A4 A5 A6 R/W
A0 A1 A2 A3 A4 A5 A6 R/W
Reserved, should be cleared
to prescale the frequency at which the digital filter takes samples from the I
rate is calculated by dividing the platform frequency by the non-zero value of DFSR. If I2C n DFSRR is cleared,
the I
1
1
2
2
2
C bus sample points default to the reset divisor 0x10.
Calling Address
Calling Address
3
3
4
4
2
C protocol. The details of the protocol are described in the following
Figure 17-8. I
5
Table 17-9. I2C n DFSRR Field Descriptions
5
6
6
7
7
Read/
Write
Read/
Write
2
C Interface Transaction Protocol
8
8
ACK
ACK
9
9
XX
Repeated
START
XX
Description
A0 A1 A2 A3 A4 A5 A6 R/W
D0 D1 D2 D3 D4 D5 D6 D7
2
1
1
C interface performs as a slave receiver after
2
2
New Calling Address
3
3
Data Byte
4
4
5
5
2
C bus. The resulting sampling
6
6
7
7
Freescale Semiconductor
8
8
No
ACK
No
ACK
9
9
STOP
STOP