MPC8313ZQADDC Freescale Semiconductor, MPC8313ZQADDC Datasheet - Page 539

• Manufacturer Part Number: MPC8313ZQADDC
• Description: Microprocessors - MPU 8313 REV2.2 PB NO ENC
• Manufacturer: Freescale Semiconductor

Specifications of MPC8313ZQADDC

• Processor Series: MPC8313
• Core: e300
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 133 MHz
• Program Memory Size: 16 KB
• Data Ram Size: 16 KB
• Interface Type: I2C
• Mounting Style: SMD/SMT
• Package / Case: PBGA
• Number Of Programmable I/os: 32
• Number Of Timers: 4

10.5.2
Because the local bus uses multiplexed address and data, special consideration must be given to avoid bus
contention at bus turnaround. The following cases must be examined:
The bus does not change direction for the following cases so they need no special attention:
10.5.2.1
During a read cycle, the memory/peripheral drives the bus and the bus transceiver drives LAD. After the
data has been sampled, the output drivers of the external device must be disabled. This can take some time;
for slow devices the EHTR feature of the GPCM or the programmability of the UPM should be used to
guarantee that those devices have stopped driving the bus when the eLBC memory controller ends the bus
cycle.
In this case, after the previous cycle ends, LBCTL goes high and changes the direction of the bus
transceiver. The eLBC then inserts a bus turnaround cycle to avoid contention. The external device has
now already placed its data signals in high impedance and no bus contention will occur.
10.5.2.2
During the address phase, LAD actively drives the address and LBCTL is high, driving the bus
transceivers in the same direction as during a write. After the end of the address phase, LBCTL goes low
and changes the direction of the bus transceiver. The eLBC places the LAD signals in high impedance after
its t
the transceiver starts to drive those signals after its t
ensure, that [t
Freescale Semiconductor
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•
•
•
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dis
(LB). The LBCTL will have its new state after t
Address phase after previous read
Read data phase after address phase
Read-modify-write cycle for parity protected memory banks
UPM cycles with additional address phases
Continued burst after the first beat
Write data phase after address phase
Address phase after previous write
Bus Turnaround
Address Phase after Previous Read
Read Data Phase after Address Phase
en
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
Local Bus Interface
(LB) + t
en
LAD[0:15]
(transceiver)] is larger than t
LBCTL
Figure 10-73. GPCM Data Timings
Muxed Address/Data
Buffered Data
Buffer
en
(transceiver) time. The system designer has to
en
dis
(LB) and, because this is an asynchronous input,
(LB) to avoid bus contention.
D
Device
Input
Pin
Enhanced Local Bus Controller
Peripherals
Memories
Slower
and
10-91