MPC8313ZQADDC Freescale Semiconductor, MPC8313ZQADDC Datasheet - Page 313

• Manufacturer Part Number: MPC8313ZQADDC
• Description: Microprocessors - MPU 8313 REV2.2 PB NO ENC
• Manufacturer: Freescale Semiconductor

Specifications of MPC8313ZQADDC

• Processor Series: MPC8313
• Core: e300
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 133 MHz
• Program Memory Size: 16 KB
• Data Ram Size: 16 KB
• Interface Type: I2C
• Mounting Style: SMD/SMT
• Package / Case: PBGA
• Number Of Programmable I/os: 32
• Number Of Timers: 4

Figure 6-9
arbitration.
A master has to acquire address bus ownership before it starts any transaction. The master asserts its own
bus request signal along with the arbitration attribute signals REPEAT & PRIORITY[0:1]. The arbiter later
asserts the corresponding address bus grant signal to the requesting master depending on the system states
and arbitration scheme. See
on arbitration scheme. When address bus grant is received the master can start the address tenure.
6.3.1.1
Whenever a master asserts its bus request to acquire address bus ownership, it can drive its
PRIORITY[0:1] signals to indicate request priority. The master would be served sooner because of its
higher priority level. The arbiter takes this extra information into consideration in order to yield better
service for a higher priority request than a lower priority request. Therefore, the arbiter operates according
to the following priority based arbitration scheme:
Figure 6-10
example, if all masters request the bus continuously, the following order of bus grants occurs with the
specific bandwidth:
Freescale Semiconductor
1. For every priority level a fair arbitration scheme is used (a simple round robin scheme)
2. For every priority level other than 0, one place is reserved as a place holder for lower level
3. Each master can change its priority level at any time.
•
•
arbitration rings.
M6 gets 1/2 of the bus bandwidth
M4 and M5 each gets 1/6 of the bus bandwidth
shows the interface signals between the arbiter and masters that are involved in address bus
shows an example of priority-based arbitration algorithm with four priority levels. In this
Address Bus Arbitration with PRIORITY[0:1]
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
Master N
Master 1
Master 2
Section 6.3.1.1, “Address Bus Arbitration with PRIORITY[0:1],”
•
•
•
Figure 6-9. Address Bus Arbitration
PRIORITY[0:1]
PRIORITY[0:1]
PRIORITY[0:1]
REPEAT
REPEAT
REPEAT
BG
BG
BG
BR
BR
BR
Arbiter
Arbiter and Bus Monitor
for details
6-11