MPC8313ZQADDC Freescale Semiconductor, MPC8313ZQADDC Datasheet - Page 247

• Manufacturer Part Number: MPC8313ZQADDC
• Description: Microprocessors - MPU 8313 REV2.2 PB NO ENC
• Manufacturer: Freescale Semiconductor

Specifications of MPC8313ZQADDC

• Processor Series: MPC8313
• Core: e300
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 133 MHz
• Program Memory Size: 16 KB
• Data Ram Size: 16 KB
• Interface Type: I2C
• Mounting Style: SMD/SMT
• Package / Case: PBGA
• Number Of Programmable I/os: 32
• Number Of Timers: 4

Table 5-40
5.5.5.2
The real time counter load register (RTLDR), shown in
in the 32-bit RTC counter.
Table 5-41
Freescale Semiconductor
26–29
Offset 0x04
Reset
0–23
0–31
Bits
Bits
24
25
30
31
W
R
0
Name
CLEN Clock enable control bit.
Name
CLDV
CLIN
AIM
SIM
—
—
defines the bit fields of RTCNR.
defines the bit fields of RTLDR.
Real Time Counter Load Register (RTLDR)
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
Write reserved, read = 0
This bit controls the counting of the RTC. When the RTC’s clock is disabled, the counter maintains its old
value. When the counter’s clock is enabled, it continues counting using the previous value.
0 Disable counter.
1 Enable counter.
Input clock control bit.
The input clock to the RTC may be either the CSB clock or an external RTC clock.
0 The input clock to the periodic interrupt timer is CSB input clock.
1 The input clock to the periodic interrupt timer is the external RTC clock.
Write reserved, read = 0
Alarm interrupt mask bit.
Used to enable or disable (mask) the RTC alarm interrupt when the RTC’s 32-bit counter reaches
RTALR[ALR] value.
0 Alarm interrupt generation disabled.
1 Alarm interrupt generation enabled.
Second interrupt mask bit.
Used to enable or disable (mask) the RTC periodic interrupt.
0 Periodic interrupt generation disabled.
1 Periodic interrupt generation enabled.
Contains the 32-bit value to be loaded in the 32-bit RTC counter.
Figure 5-26. Real Time Counter Load Register (RTLDR)
Table 5-40. RTCNR Bit Settings
Table 5-41. RTLDR Bit Settings
All zeros
CLDV
Figure
Description
Description
5-26, contains the 32-bit value to be loaded
System Configuration
Access: Read/Write
5-39
31