MPC8313ZQADDC Freescale Semiconductor, MPC8313ZQADDC Datasheet - Page 220

• Manufacturer Part Number: MPC8313ZQADDC
• Description: Microprocessors - MPU 8313 REV2.2 PB NO ENC
• Manufacturer: Freescale Semiconductor

Specifications of MPC8313ZQADDC

• Processor Series: MPC8313
• Core: e300
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 133 MHz
• Program Memory Size: 16 KB
• Data Ram Size: 16 KB
• Interface Type: I2C
• Mounting Style: SMD/SMT
• Package / Case: PBGA
• Number Of Programmable I/os: 32
• Number Of Timers: 4

System Configuration
5.2.4.7
The DDR local access window n base address registers (DDRLAWBAR0–DDRLAWBAR1) are shown
in
Table 5-15
5.2.4.7.1
The core may use a DDR SDRAM device to fetch its boot vector. For this purpose, the
DDRLAWBAR0[BASE_ADDR] reset value is set according to the value set in the reset configuration
word high BMS field.
Table 5-16
5-12
1
20–31
‘
The reset value of DDRLAWBAR0[BASE_ADDR] depends on the reset configuration word high values. See
“DDRLAWBAR0[BASE_ADDR] Reset Value ,”
0–19
Figure
Bits
Offset 0xA0
Reset
Figure 5-8. DDR Local Access Window n Base Address Registers (DDRLAWBAR0–DDRLAWBAR1)
W
R
0xA8
5-8.
0
BASE_ADDR
defines the bit fields of DDRLAWBAR0
defines the reset value DDRLAWBAR0.
DDR Local Access Window n Base Address Registers
(DDRLAWBAR0–DDRLAWBAR1)
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
Name
DDRLAWBAR0[BASE_ADDR] Reset Value
—
base address should be aligned to the window size, as defined by DDRLAWAR n [SIZE].
Reserved. Write has no effect, read returns 0.
Identifies the 20 most-significant address bits of the base of local access window n . The specified
Table 5-15. DDRLAWBAR0–DDRLAWBAR1 Bit Settings
Table 5-16. DDRLAWBAR0[BASE_ADDR] Reset Value
RCWHR[BMS]
BASE_ADDR
0
1
for a detailed description
DDRLAWBAR0[BASE_ADDR]
–
All zeros
DDRLAWBAR1.
Reset Value
0xFF800
0x00000
Description
1
19 20
Freescale Semiconductor
—
Access: Read/Write
Section 5.2.4.7.1,
31