MPC8313ZQADDC Freescale Semiconductor, MPC8313ZQADDC Datasheet - Page 393

• Manufacturer Part Number: MPC8313ZQADDC
• Description: Microprocessors - MPU 8313 REV2.2 PB NO ENC
• Manufacturer: Freescale Semiconductor

Specifications of MPC8313ZQADDC

• Processor Series: MPC8313
• Core: e300
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 133 MHz
• Program Memory Size: 16 KB
• Data Ram Size: 16 KB
• Interface Type: I2C
• Mounting Style: SMD/SMT
• Package / Case: PBGA
• Number Of Programmable I/os: 32
• Number Of Timers: 4

Figure 8-26
8.6.8
Pending unmasked interrupts are presented to the core in order of priority according to
interrupt vector that allows the core to locate the interrupt service routine is made available to the core by
interrupt handler software reading SIVCR. The interrupt controller passes an interrupt vector
corresponding to the highest-priority, unmasked, pending interrupt in response to a read of SIVCR.
Table 8-5
8.6.9
The PIC supports the non-maskable machine check interrupts. When an error interrupt signal is received,
the interrupt controller indicates the source by setting the corresponding SERSR bit. These sources are
listed in
Freescale Semiconductor
Event
Mask
Table
Bit
Bit
lists the encodings for the seven low-order bits of the interrupt vector.
DDR MASK
DDR EVENT
Interrupt Vector Generation and Calculation
Machine Check Interrupts
shows an example of how the masking occurs, using a DDR block as an example.
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
8-21.
Figure 8-26. DDR Interrupt Request Masking
XX Input (or
XX Event Bits)
Mask
Bit
SIPNR
SIMSR
Integrated Programmable Interrupt Controller (IPIC)
(Other Unmasked Requests)
Table
Request to
the core
8-31. The
8-35