MPC8313ZQADDC Freescale Semiconductor, MPC8313ZQADDC Datasheet - Page 1137

• Manufacturer Part Number: MPC8313ZQADDC
• Description: Microprocessors - MPU 8313 REV2.2 PB NO ENC
• Manufacturer: Freescale Semiconductor

Specifications of MPC8313ZQADDC

• Processor Series: MPC8313
• Core: e300
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 133 MHz
• Program Memory Size: 16 KB
• Data Ram Size: 16 KB
• Interface Type: I2C
• Mounting Style: SMD/SMT
• Package / Case: PBGA
• Number Of Programmable I/os: 32
• Number Of Timers: 4

Serial Peripheral Interface
Transmission continues until no more data is available or SPISEL is negated. Transmission continues once
SPISEL is reasserted and SPICLK begins toggling. After the characters in the buffer are sent, the SPI sends
one as long as SPISEL remains asserted.
19.2.3.3
SPI in Multiple-Master Operation
The SPI can operate in a multiple-master environment in which all SPI devices are connected to the same
bus. In this configuration, the SPIMOSI, SPIMISO, and SPICLK signals of all SPIs are shared; but the
SPISEL inputs are connected separately, as shown in
Figure
19-3. Only one SPI device can act as master
at a time—all others must be slaves. When a SPI is configured as a master, if its SPISEL input is asserted,
a multiple-master error occurs because more than one SPI device is a bus master. The SPI sets SPIE[MME]
in the SPI event register and a maskable interrupt is issued to the core. It also disables SPI operation and
the output drivers of the SPI signals. The core must clear SPMODE[EN], correct the problems, and clear
SPIE[MME] before the SPI can be used again.
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
Freescale Semiconductor
19-5